494 			   unsigned long rate, unsigned long parent_rate)  in _get_table_rate()  argument
501 		if (sel->input_rate == parent_rate &&  in _get_table_rate()
528 		      unsigned long rate, unsigned long parent_rate)  in _calc_rate()  argument
535 	switch (parent_rate) {  in _calc_rate()
552 		cfreq = parent_rate / (parent_rate / 1000000);  in _calc_rate()
556 		       __func__, parent_rate);  in _calc_rate()
565 	cfg->m = parent_rate / cfreq;  in _calc_rate()
780 			unsigned long parent_rate)  in clk_pll_set_rate()  argument
797 	if (_get_table_rate(hw, &cfg, rate, parent_rate) &&  in clk_pll_set_rate()
798 	    pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {  in clk_pll_set_rate()
842 					 unsigned long parent_rate)  in clk_pll_recalc_rate()  argument
847 	u64 rate = parent_rate;  in clk_pll_recalc_rate()
853 		return parent_rate;  in clk_pll_recalc_rate()
860 					parent_rate)) {  in clk_pll_recalc_rate()
990 					 unsigned long parent_rate)  in clk_plle_recalc_rate()  argument
995 	u64 rate = parent_rate;  in clk_plle_recalc_rate()
1151 			   unsigned long parent_rate)  in _pll_fixed_mdiv()  argument
1153 	u16 mdiv = parent_rate / pll_params->cf_min;  in _pll_fixed_mdiv()
1162 	if (parent_rate > pll_params->cf_max)  in _pll_fixed_mdiv()
1170 				unsigned long rate, unsigned long parent_rate)  in _calc_dynamic_ramp_rate()  argument
1180 	cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);  in _calc_dynamic_ramp_rate()
1182 	cfg->n = cfg->output_rate * cfg->m / parent_rate;  in _calc_dynamic_ramp_rate()
1183 	cfg->input_rate = parent_rate;  in _calc_dynamic_ramp_rate()
1210 				   unsigned long parent_rate)  in _clip_vco_min()  argument
1212 	return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;  in _clip_vco_min()
1217 			       unsigned long parent_rate)  in _setup_dynamic_ramp()  argument
1222 	switch (parent_rate) {  in _setup_dynamic_ramp()
1239 			__func__, parent_rate);  in _setup_dynamic_ramp()
1253 			      unsigned long rate, unsigned long parent_rate)  in _pll_ramp_calc_pll()  argument
1258 	err = _get_table_rate(hw, cfg, rate, parent_rate);  in _pll_ramp_calc_pll()
1260 		err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);  in _pll_ramp_calc_pll()
1262 		if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {  in _pll_ramp_calc_pll()
1277 				unsigned long parent_rate)  in clk_pllxc_set_rate()  argument
1284 	ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);  in clk_pllxc_set_rate()
1432 				unsigned long parent_rate)  in clk_pllc_set_rate()  argument
1442 	ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);  in clk_pllc_set_rate()
1460 	ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);  in clk_pllc_set_rate()
1478 			     unsigned long rate, unsigned long parent_rate)  in _pllre_calc_rate()  argument
1481 	u64 output_rate = parent_rate;  in _pllre_calc_rate()
1483 	m = _pll_fixed_mdiv(pll->params, parent_rate);  in _pllre_calc_rate()
1484 	n = rate * m / parent_rate;  in _pllre_calc_rate()
1498 				unsigned long parent_rate)  in clk_pllre_set_rate()  argument
1508 	_pllre_calc_rate(pll, &cfg, rate, parent_rate);  in clk_pllre_set_rate()
1532 					 unsigned long parent_rate)  in clk_pllre_recalc_rate()  argument
1536 	u64 rate = parent_rate;  in clk_pllre_recalc_rate()
1971 	unsigned long parent_rate;  in tegra_clk_register_pllxc()  local
1984 	parent_rate = clk_get_rate(parent);  in tegra_clk_register_pllxc()
1986 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllxc()
1990 							     parent_rate);  in tegra_clk_register_pllxc()
1999 		err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);  in tegra_clk_register_pllxc()
2031 			  spinlock_t *lock, unsigned long parent_rate)  in tegra_clk_register_pllre()  argument
2037 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllre()
2041 							     parent_rate);  in tegra_clk_register_pllre()
2056 		m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllre()
2058 		val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);  in tegra_clk_register_pllre()
2084 	unsigned long parent_rate;  in tegra_clk_register_pllm()  local
2096 	parent_rate = clk_get_rate(parent);  in tegra_clk_register_pllm()
2098 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllm()
2102 							     parent_rate);  in tegra_clk_register_pllm()
2128 	unsigned long parent_rate;  in tegra_clk_register_pllc()  local
2140 	parent_rate = clk_get_rate(parent);  in tegra_clk_register_pllc()
2142 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllc()
2158 	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllc()
2159 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllc()
2182 	_pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);  in tegra_clk_register_pllc()
2272 	unsigned long parent_rate;  in tegra_clk_register_pllss()  local
2294 	parent_rate = clk_get_rate(parent);  in tegra_clk_register_pllss()
2296 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllss()
2300 	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllss()
2301 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllss()
2350 			  spinlock_t *lock, unsigned long parent_rate)  in tegra_clk_register_pllre_tegra210()  argument
2356 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllre_tegra210()
2360 							     parent_rate);  in tegra_clk_register_pllre_tegra210()
2727 	unsigned long parent_rate;  in tegra_clk_register_pllc_tegra210()  local
2739 	parent_rate = clk_get_rate(parent);  in tegra_clk_register_pllc_tegra210()
2741 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllc_tegra210()
2745 							     parent_rate);  in tegra_clk_register_pllc_tegra210()
2768 	unsigned long parent_rate;  in tegra_clk_register_pllxc_tegra210()  local
2780 	parent_rate = clk_get_rate(parent);  in tegra_clk_register_pllxc_tegra210()
2782 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllxc_tegra210()
2786 							     parent_rate);  in tegra_clk_register_pllxc_tegra210()
2809 	unsigned long parent_rate;  in tegra_clk_register_pllss_tegra210()  local
2831 	parent_rate = clk_get_rate(parent);  in tegra_clk_register_pllss_tegra210()
2833 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllss_tegra210()
2837 							     parent_rate);  in tegra_clk_register_pllss_tegra210()
2841 	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllss_tegra210()
2842 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllss_tegra210()
2887 	unsigned long parent_rate;  in tegra_clk_register_pllmb()  local
2899 	parent_rate = clk_get_rate(parent);  in tegra_clk_register_pllmb()
2901 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllmb()
2905 							     parent_rate);  in tegra_clk_register_pllmb()