Lines Matching refs:_parent
17 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
21 .parent_names = (const char *[]) { _parent }, \
58 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
65 .hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \
69 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
70 ZX_PLL(_name, _parent, _reg, _table, 0, 30)
77 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
85 _parent, \
97 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \ argument
103 _parent, \
115 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
124 _parent, \
131 #define MUX(_id, _name, _parent, _reg, _shift, _width) \ argument
132 MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
139 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \ argument
149 _parent, \