Lines Matching refs:reg_width
748 unsigned int reg_width; in dwc_prep_slave_sg() local
766 reg_width = __ffs(sconfig->dst_addr_width); in dwc_prep_slave_sg()
769 | DWC_CTLL_DST_WIDTH(reg_width) in dwc_prep_slave_sg()
819 reg_width = __ffs(sconfig->src_addr_width); in dwc_prep_slave_sg()
822 | DWC_CTLL_SRC_WIDTH(reg_width) in dwc_prep_slave_sg()
846 if ((len >> reg_width) > dwc->block_size) { in dwc_prep_slave_sg()
847 dlen = dwc->block_size << reg_width; in dwc_prep_slave_sg()
854 lli_write(desc, ctlhi, dlen >> reg_width); in dwc_prep_slave_sg()
1262 unsigned int reg_width; in dw_dma_cyclic_prep() local
1298 reg_width = __ffs(sconfig->dst_addr_width); in dw_dma_cyclic_prep()
1300 reg_width = __ffs(sconfig->src_addr_width); in dw_dma_cyclic_prep()
1305 if (period_len > (dwc->block_size << reg_width)) in dw_dma_cyclic_prep()
1307 if (unlikely(period_len & ((1 << reg_width) - 1))) in dw_dma_cyclic_prep()
1309 if (unlikely(buf_addr & ((1 << reg_width) - 1))) in dw_dma_cyclic_prep()
1332 | DWC_CTLL_DST_WIDTH(reg_width) in dw_dma_cyclic_prep()
1333 | DWC_CTLL_SRC_WIDTH(reg_width) in dw_dma_cyclic_prep()
1347 | DWC_CTLL_SRC_WIDTH(reg_width) in dw_dma_cyclic_prep()
1348 | DWC_CTLL_DST_WIDTH(reg_width) in dw_dma_cyclic_prep()
1362 lli_write(desc, ctlhi, period_len >> reg_width); in dw_dma_cyclic_prep()