Lines Matching refs:gpio
152 struct zynq_gpio *gpio) in zynq_gpio_get_bank_pin() argument
156 for (bank = 0; bank < gpio->p_data->max_bank; bank++) { in zynq_gpio_get_bank_pin()
157 if ((pin_num >= gpio->p_data->bank_min[bank]) && in zynq_gpio_get_bank_pin()
158 (pin_num <= gpio->p_data->bank_max[bank])) { in zynq_gpio_get_bank_pin()
161 gpio->p_data->bank_min[bank]; in zynq_gpio_get_bank_pin()
185 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_get_value() local
187 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_get_value()
189 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
209 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_set_value() local
211 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_set_value()
229 writel_relaxed(state, gpio->base_addr + reg_offset); in zynq_gpio_set_value()
247 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_dir_in() local
249 is_zynq_gpio = gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_FOO; in zynq_gpio_dir_in()
250 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_dir_in()
261 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
263 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
285 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_dir_out() local
287 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_dir_out()
290 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
292 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
295 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
297 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
315 struct zynq_gpio *gpio = in zynq_gpio_irq_mask() local
319 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_irq_mask()
321 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); in zynq_gpio_irq_mask()
336 struct zynq_gpio *gpio = in zynq_gpio_irq_unmask() local
340 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_irq_unmask()
342 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); in zynq_gpio_irq_unmask()
356 struct zynq_gpio *gpio = in zynq_gpio_irq_ack() local
360 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_irq_ack()
362 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); in zynq_gpio_irq_ack()
407 struct zynq_gpio *gpio = in zynq_gpio_set_irq_type() local
411 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_set_irq_type()
413 int_type = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
415 int_pol = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
417 int_any = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
452 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
454 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
456 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
471 struct zynq_gpio *gpio = in zynq_gpio_set_wake() local
474 irq_set_irq_wake(gpio->irq, on); in zynq_gpio_set_wake()
503 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio, in zynq_gpio_handle_bank_irq() argument
507 unsigned int bank_offset = gpio->p_data->bank_min[bank_num]; in zynq_gpio_handle_bank_irq()
508 struct irq_domain *irqdomain = gpio->chip.irqdomain; in zynq_gpio_handle_bank_irq()
537 struct zynq_gpio *gpio = in zynq_gpio_irqhandler() local
543 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { in zynq_gpio_irqhandler()
544 int_sts = readl_relaxed(gpio->base_addr + in zynq_gpio_irqhandler()
546 int_enb = readl_relaxed(gpio->base_addr + in zynq_gpio_irqhandler()
548 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb); in zynq_gpio_irqhandler()
581 struct zynq_gpio *gpio = platform_get_drvdata(pdev); in zynq_gpio_runtime_suspend() local
583 clk_disable_unprepare(gpio->clk); in zynq_gpio_runtime_suspend()
591 struct zynq_gpio *gpio = platform_get_drvdata(pdev); in zynq_gpio_runtime_resume() local
593 return clk_prepare_enable(gpio->clk); in zynq_gpio_runtime_resume()
675 struct zynq_gpio *gpio; in zynq_gpio_probe() local
680 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in zynq_gpio_probe()
681 if (!gpio) in zynq_gpio_probe()
689 gpio->p_data = match->data; in zynq_gpio_probe()
690 platform_set_drvdata(pdev, gpio); in zynq_gpio_probe()
693 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res); in zynq_gpio_probe()
694 if (IS_ERR(gpio->base_addr)) in zynq_gpio_probe()
695 return PTR_ERR(gpio->base_addr); in zynq_gpio_probe()
697 gpio->irq = platform_get_irq(pdev, 0); in zynq_gpio_probe()
698 if (gpio->irq < 0) { in zynq_gpio_probe()
700 return gpio->irq; in zynq_gpio_probe()
704 chip = &gpio->chip; in zynq_gpio_probe()
705 chip->label = gpio->p_data->label; in zynq_gpio_probe()
715 chip->ngpio = gpio->p_data->ngpio; in zynq_gpio_probe()
718 gpio->clk = devm_clk_get(&pdev->dev, NULL); in zynq_gpio_probe()
719 if (IS_ERR(gpio->clk)) { in zynq_gpio_probe()
721 return PTR_ERR(gpio->clk); in zynq_gpio_probe()
723 ret = clk_prepare_enable(gpio->clk); in zynq_gpio_probe()
736 ret = gpiochip_add_data(chip, gpio); in zynq_gpio_probe()
743 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) in zynq_gpio_probe()
744 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + in zynq_gpio_probe()
754 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq, in zynq_gpio_probe()
767 clk_disable_unprepare(gpio->clk); in zynq_gpio_probe()
780 struct zynq_gpio *gpio = platform_get_drvdata(pdev); in zynq_gpio_remove() local
783 gpiochip_remove(&gpio->chip); in zynq_gpio_remove()
784 clk_disable_unprepare(gpio->clk); in zynq_gpio_remove()