Lines Matching refs:performance_level_count

951 		for (i = 0; i < ps->performance_level_count; i++) {  in ci_apply_state_adjust_rules()
962 		mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;  in ci_apply_state_adjust_rules()
3875 	if (state->performance_level_count < 1)  in ci_trim_dpm_states()
3878 	if (state->performance_level_count == 1)  in ci_trim_dpm_states()
3982 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_find_dpm_states_clocks_in_dpm_table()
3984 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_find_dpm_states_clocks_in_dpm_table()
4020 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4021 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4933 	for (i = 0; i < state->performance_level_count; i++) {  in ci_get_maximum_link_speed()
5562 	ps->performance_level_count = index + 1;  in ci_parse_pplib_clock_info()
6095 	for (i = 0; i < ps->performance_level_count; i++) {  in ci_dpm_print_power_state()
6111 		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;  in ci_dpm_get_sclk()
6122 		return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;  in ci_dpm_get_mclk()
6573 	ps->performance_levels[ps->performance_level_count - 1].sclk =  in ci_dpm_set_sclk_od()
6607 	ps->performance_levels[ps->performance_level_count - 1].mclk =  in ci_dpm_set_mclk_od()