Lines Matching refs:ih
67 adev->irq.ih.enabled = true; in cik_ih_enable_interrupts()
89 adev->irq.ih.enabled = false; in cik_ih_disable_interrupts()
90 adev->irq.ih.rptr = 0; in cik_ih_disable_interrupts()
124 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cik_ih_irq_init()
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
134 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in cik_ih_irq_init()
190 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in cik_ih_get_wptr()
199 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in cik_ih_get_wptr()
200 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in cik_ih_get_wptr()
205 return (wptr & adev->irq.ih.ptr_mask); in cik_ih_get_wptr()
243 u32 ring_index = adev->irq.ih.rptr >> 2; in cik_ih_decode_iv()
246 dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); in cik_ih_decode_iv()
247 dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); in cik_ih_decode_iv()
248 dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); in cik_ih_decode_iv()
249 dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); in cik_ih_decode_iv()
258 adev->irq.ih.rptr += 16; in cik_ih_decode_iv()
270 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); in cik_ih_set_rptr()