Lines Matching refs:ih
67 adev->irq.ih.enabled = true; in iceland_ih_enable_interrupts()
89 adev->irq.ih.enabled = false; in iceland_ih_disable_interrupts()
90 adev->irq.ih.rptr = 0; in iceland_ih_disable_interrupts()
125 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in iceland_ih_irq_init()
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
136 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in iceland_ih_irq_init()
192 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in iceland_ih_get_wptr()
201 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in iceland_ih_get_wptr()
202 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in iceland_ih_get_wptr()
207 return (wptr & adev->irq.ih.ptr_mask); in iceland_ih_get_wptr()
222 u32 ring_index = adev->irq.ih.rptr >> 2; in iceland_ih_decode_iv()
225 dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); in iceland_ih_decode_iv()
226 dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); in iceland_ih_decode_iv()
227 dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); in iceland_ih_decode_iv()
228 dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); in iceland_ih_decode_iv()
237 adev->irq.ih.rptr += 16; in iceland_ih_decode_iv()
249 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); in iceland_ih_set_rptr()