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Lines Matching refs:ring

53 static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)  in uvd_v6_0_ring_get_rptr()  argument
55 struct amdgpu_device *adev = ring->adev; in uvd_v6_0_ring_get_rptr()
67 static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring) in uvd_v6_0_ring_get_wptr() argument
69 struct amdgpu_device *adev = ring->adev; in uvd_v6_0_ring_get_wptr()
81 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring) in uvd_v6_0_ring_set_wptr() argument
83 struct amdgpu_device *adev = ring->adev; in uvd_v6_0_ring_set_wptr()
85 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); in uvd_v6_0_ring_set_wptr()
104 struct amdgpu_ring *ring; in uvd_v6_0_sw_init() local
121 ring = &adev->uvd.ring; in uvd_v6_0_sw_init()
122 sprintf(ring->name, "uvd"); in uvd_v6_0_sw_init()
123 r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, in uvd_v6_0_sw_init()
155 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v6_0_hw_init() local
163 ring->ready = true; in uvd_v6_0_hw_init()
164 r = amdgpu_ring_test_ring(ring); in uvd_v6_0_hw_init()
166 ring->ready = false; in uvd_v6_0_hw_init()
170 r = amdgpu_ring_alloc(ring, 10); in uvd_v6_0_hw_init()
177 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
178 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
181 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
182 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
185 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
186 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init()
190 amdgpu_ring_write(ring, 0x8); in uvd_v6_0_hw_init()
192 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()
193 amdgpu_ring_write(ring, 3); in uvd_v6_0_hw_init()
195 amdgpu_ring_commit(ring); in uvd_v6_0_hw_init()
214 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v6_0_hw_fini() local
217 ring->ready = false; in uvd_v6_0_hw_fini()
388 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v6_0_start() local
501 rb_bufsz = order_base_2(ring->ring_size); in uvd_v6_0_start()
514 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); in uvd_v6_0_start()
518 lower_32_bits(ring->gpu_addr)); in uvd_v6_0_start()
520 upper_32_bits(ring->gpu_addr)); in uvd_v6_0_start()
525 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v6_0_start()
526 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); in uvd_v6_0_start()
568 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, in uvd_v6_0_ring_emit_fence() argument
573 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v6_0_ring_emit_fence()
574 amdgpu_ring_write(ring, seq); in uvd_v6_0_ring_emit_fence()
575 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_fence()
576 amdgpu_ring_write(ring, addr & 0xffffffff); in uvd_v6_0_ring_emit_fence()
577 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_fence()
578 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v6_0_ring_emit_fence()
579 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_fence()
580 amdgpu_ring_write(ring, 0); in uvd_v6_0_ring_emit_fence()
582 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_fence()
583 amdgpu_ring_write(ring, 0); in uvd_v6_0_ring_emit_fence()
584 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_fence()
585 amdgpu_ring_write(ring, 0); in uvd_v6_0_ring_emit_fence()
586 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_fence()
587 amdgpu_ring_write(ring, 2); in uvd_v6_0_ring_emit_fence()
597 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) in uvd_v6_0_ring_emit_hdp_flush() argument
599 amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); in uvd_v6_0_ring_emit_hdp_flush()
600 amdgpu_ring_write(ring, 0); in uvd_v6_0_ring_emit_hdp_flush()
610 static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) in uvd_v6_0_ring_emit_hdp_invalidate() argument
612 amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); in uvd_v6_0_ring_emit_hdp_invalidate()
613 amdgpu_ring_write(ring, 1); in uvd_v6_0_ring_emit_hdp_invalidate()
623 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring) in uvd_v6_0_ring_test_ring() argument
625 struct amdgpu_device *adev = ring->adev; in uvd_v6_0_ring_test_ring()
631 r = amdgpu_ring_alloc(ring, 3); in uvd_v6_0_ring_test_ring()
634 ring->idx, r); in uvd_v6_0_ring_test_ring()
637 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v6_0_ring_test_ring()
638 amdgpu_ring_write(ring, 0xDEADBEEF); in uvd_v6_0_ring_test_ring()
639 amdgpu_ring_commit(ring); in uvd_v6_0_ring_test_ring()
649 ring->idx, i); in uvd_v6_0_ring_test_ring()
652 ring->idx, tmp); in uvd_v6_0_ring_test_ring()
666 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring, in uvd_v6_0_ring_emit_ib() argument
670 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0)); in uvd_v6_0_ring_emit_ib()
671 amdgpu_ring_write(ring, vm_id); in uvd_v6_0_ring_emit_ib()
673 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); in uvd_v6_0_ring_emit_ib()
674 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v6_0_ring_emit_ib()
675 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); in uvd_v6_0_ring_emit_ib()
676 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in uvd_v6_0_ring_emit_ib()
677 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); in uvd_v6_0_ring_emit_ib()
678 amdgpu_ring_write(ring, ib->length_dw); in uvd_v6_0_ring_emit_ib()
681 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, in uvd_v6_0_ring_emit_vm_flush() argument
691 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_vm_flush()
692 amdgpu_ring_write(ring, reg << 2); in uvd_v6_0_ring_emit_vm_flush()
693 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_vm_flush()
694 amdgpu_ring_write(ring, pd_addr >> 12); in uvd_v6_0_ring_emit_vm_flush()
695 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_vm_flush()
696 amdgpu_ring_write(ring, 0x8); in uvd_v6_0_ring_emit_vm_flush()
698 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_vm_flush()
699 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); in uvd_v6_0_ring_emit_vm_flush()
700 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_vm_flush()
701 amdgpu_ring_write(ring, 1 << vm_id); in uvd_v6_0_ring_emit_vm_flush()
702 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_vm_flush()
703 amdgpu_ring_write(ring, 0x8); in uvd_v6_0_ring_emit_vm_flush()
705 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_vm_flush()
706 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); in uvd_v6_0_ring_emit_vm_flush()
707 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_vm_flush()
708 amdgpu_ring_write(ring, 0); in uvd_v6_0_ring_emit_vm_flush()
709 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); in uvd_v6_0_ring_emit_vm_flush()
710 amdgpu_ring_write(ring, 1 << vm_id); /* mask */ in uvd_v6_0_ring_emit_vm_flush()
711 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_vm_flush()
712 amdgpu_ring_write(ring, 0xC); in uvd_v6_0_ring_emit_vm_flush()
715 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) in uvd_v6_0_ring_emit_pipeline_sync() argument
717 uint32_t seq = ring->fence_drv.sync_seq; in uvd_v6_0_ring_emit_pipeline_sync()
718 uint64_t addr = ring->fence_drv.gpu_addr; in uvd_v6_0_ring_emit_pipeline_sync()
720 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
721 amdgpu_ring_write(ring, lower_32_bits(addr)); in uvd_v6_0_ring_emit_pipeline_sync()
722 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
723 amdgpu_ring_write(ring, upper_32_bits(addr)); in uvd_v6_0_ring_emit_pipeline_sync()
724 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
725 amdgpu_ring_write(ring, 0xffffffff); /* mask */ in uvd_v6_0_ring_emit_pipeline_sync()
726 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
727 amdgpu_ring_write(ring, seq); in uvd_v6_0_ring_emit_pipeline_sync()
728 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
729 amdgpu_ring_write(ring, 0xE); in uvd_v6_0_ring_emit_pipeline_sync()
732 static unsigned uvd_v6_0_ring_get_emit_ib_size(struct amdgpu_ring *ring) in uvd_v6_0_ring_get_emit_ib_size() argument
738 static unsigned uvd_v6_0_ring_get_dma_frame_size(struct amdgpu_ring *ring) in uvd_v6_0_ring_get_dma_frame_size() argument
747 static unsigned uvd_v6_0_ring_get_dma_frame_size_vm(struct amdgpu_ring *ring) in uvd_v6_0_ring_get_dma_frame_size_vm() argument
865 amdgpu_fence_process(&adev->uvd.ring); in uvd_v6_0_process_interrupt()
1097 adev->uvd.ring.funcs = &uvd_v6_0_ring_vm_funcs; in uvd_v6_0_set_ring_funcs()
1100 adev->uvd.ring.funcs = &uvd_v6_0_ring_phys_funcs; in uvd_v6_0_set_ring_funcs()