Lines Matching refs:hwmgr
48 static uint16_t get_vce_table_offset(struct pp_hwmgr *hwmgr, in get_vce_table_offset() argument
72 static uint16_t get_vce_clock_info_array_offset(struct pp_hwmgr *hwmgr, in get_vce_clock_info_array_offset() argument
75 uint16_t table_offset = get_vce_table_offset(hwmgr, in get_vce_clock_info_array_offset()
84 static uint16_t get_vce_clock_info_array_size(struct pp_hwmgr *hwmgr, in get_vce_clock_info_array_size() argument
87 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr, in get_vce_clock_info_array_size()
100 static uint16_t get_vce_clock_voltage_limit_table_offset(struct pp_hwmgr *hwmgr, in get_vce_clock_voltage_limit_table_offset() argument
103 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr, in get_vce_clock_voltage_limit_table_offset()
107 return table_offset + get_vce_clock_info_array_size(hwmgr, in get_vce_clock_voltage_limit_table_offset()
113 static uint16_t get_vce_clock_voltage_limit_table_size(struct pp_hwmgr *hwmgr, in get_vce_clock_voltage_limit_table_size() argument
116 uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table); in get_vce_clock_voltage_limit_table_size()
128 static uint16_t get_vce_state_table_offset(struct pp_hwmgr *hwmgr, const ATOM_PPLIB_POWERPLAYTABLE … in get_vce_state_table_offset() argument
130 uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table); in get_vce_state_table_offset()
133 return table_offset + get_vce_clock_voltage_limit_table_size(hwmgr, powerplay_table); in get_vce_state_table_offset()
139 struct pp_hwmgr *hwmgr, in get_vce_state_table() argument
142 uint16_t table_offset = get_vce_state_table_offset(hwmgr, powerplay_table); in get_vce_state_table()
150 static uint16_t get_uvd_table_offset(struct pp_hwmgr *hwmgr, in get_uvd_table_offset() argument
172 static uint16_t get_uvd_clock_info_array_offset(struct pp_hwmgr *hwmgr, in get_uvd_clock_info_array_offset() argument
175 uint16_t table_offset = get_uvd_table_offset(hwmgr, in get_uvd_clock_info_array_offset()
183 static uint16_t get_uvd_clock_info_array_size(struct pp_hwmgr *hwmgr, in get_uvd_clock_info_array_size() argument
186 uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr, in get_uvd_clock_info_array_size()
202 struct pp_hwmgr *hwmgr, in get_uvd_clock_voltage_limit_table_offset() argument
205 uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr, in get_uvd_clock_voltage_limit_table_offset()
210 get_uvd_clock_info_array_size(hwmgr, powerplay_table); in get_uvd_clock_voltage_limit_table_offset()
215 static uint16_t get_samu_table_offset(struct pp_hwmgr *hwmgr, in get_samu_table_offset() argument
239 struct pp_hwmgr *hwmgr, in get_samu_clock_voltage_limit_table_offset() argument
242 uint16_t table_offset = get_samu_table_offset(hwmgr, in get_samu_clock_voltage_limit_table_offset()
251 static uint16_t get_acp_table_offset(struct pp_hwmgr *hwmgr, in get_acp_table_offset() argument
275 struct pp_hwmgr *hwmgr, in get_acp_clock_voltage_limit_table_offset() argument
278 uint16_t tableOffset = get_acp_table_offset(hwmgr, powerplay_table); in get_acp_clock_voltage_limit_table_offset()
287 struct pp_hwmgr *hwmgr, in get_cacp_tdp_table_offset() argument
310 static int get_cac_tdp_table(struct pp_hwmgr *hwmgr, in get_cac_tdp_table() argument
338 static uint16_t get_sclk_vdd_gfx_table_offset(struct pp_hwmgr *hwmgr, in get_sclk_vdd_gfx_table_offset() argument
363 struct pp_hwmgr *hwmgr, in get_sclk_vdd_gfx_clock_voltage_dependency_table_offset() argument
366 uint16_t tableOffset = get_sclk_vdd_gfx_table_offset(hwmgr, powerplay_table); in get_sclk_vdd_gfx_clock_voltage_dependency_table_offset()
375 static int get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr, in get_clock_voltage_dependency_table() argument
406 static int get_valid_clk(struct pp_hwmgr *hwmgr, in get_valid_clk() argument
428 static int get_clock_voltage_limit(struct pp_hwmgr *hwmgr, in get_clock_voltage_limit() argument
443 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable, in set_hw_cap() argument
447 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
449 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
452 static int set_platform_caps(struct pp_hwmgr *hwmgr, in set_platform_caps() argument
456 hwmgr, in set_platform_caps()
462 hwmgr, in set_platform_caps()
468 hwmgr, in set_platform_caps()
474 hwmgr, in set_platform_caps()
480 hwmgr, in set_platform_caps()
486 hwmgr, in set_platform_caps()
492 hwmgr, in set_platform_caps()
498 hwmgr, in set_platform_caps()
504 hwmgr, in set_platform_caps()
510 hwmgr, in set_platform_caps()
516 hwmgr, in set_platform_caps()
522 hwmgr, in set_platform_caps()
528 hwmgr, in set_platform_caps()
534 hwmgr, in set_platform_caps()
540 hwmgr, in set_platform_caps()
546 hwmgr, in set_platform_caps()
552 hwmgr, in set_platform_caps()
558 hwmgr, in set_platform_caps()
564 hwmgr, in set_platform_caps()
570 hwmgr, in set_platform_caps()
576 hwmgr, in set_platform_caps()
582 hwmgr, in set_platform_caps()
588 hwmgr, in set_platform_caps()
594 hwmgr, in set_platform_caps()
600 hwmgr, in set_platform_caps()
606 hwmgr, in set_platform_caps()
612 hwmgr, in set_platform_caps()
621 struct pp_hwmgr *hwmgr, in make_classification_flags() argument
678 static int init_non_clock_fields(struct pp_hwmgr *hwmgr, in init_non_clock_fields() argument
687 ps->classification.flags = make_classification_flags(hwmgr, in init_non_clock_fields()
795 struct pp_hwmgr *hwmgr) in get_powerplay_table() argument
797 const void *table_addr = hwmgr->soft_pp_table; in get_powerplay_table()
802 table_addr = cgs_atom_get_data_table(hwmgr->device, in get_powerplay_table()
806 hwmgr->soft_pp_table = table_addr; in get_powerplay_table()
807 hwmgr->soft_pp_table_size = size; in get_powerplay_table()
813 int pp_tables_get_response_times(struct pp_hwmgr *hwmgr, in pp_tables_get_response_times() argument
816 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_tab = get_powerplay_table(hwmgr); in pp_tables_get_response_times()
827 int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr, in pp_tables_get_num_of_entries() argument
831 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr); in pp_tables_get_num_of_entries()
847 int pp_tables_get_entry(struct pp_hwmgr *hwmgr, in pp_tables_get_entry() argument
856 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr); in pp_tables_get_entry()
888 result = init_non_clock_fields(hwmgr, ps, pnon_clock_arrays->ucEntrySize, pnon_clock_info); in pp_tables_get_entry()
894 res = func(hwmgr, &ps->hardware, i, pclock_info); in pp_tables_get_entry()
910 result = init_non_clock_fields(hwmgr, ps, in pp_tables_get_entry()
920 int res = func(hwmgr, &ps->hardware, i, pclock_info); in pp_tables_get_entry()
929 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware)); in pp_tables_get_entry()
937 struct pp_hwmgr *hwmgr, in init_powerplay_tables() argument
946 struct pp_hwmgr *hwmgr, in init_thermal_controller() argument
952 static int init_overdrive_limits_V1_4(struct pp_hwmgr *hwmgr, in init_overdrive_limits_V1_4() argument
956 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_overdrive_limits_V1_4()
959 hwmgr->platform_descriptor.overdriveLimit.memoryClock = in init_overdrive_limits_V1_4()
962 hwmgr->platform_descriptor.maxOverdriveVDDC = in init_overdrive_limits_V1_4()
965 hwmgr->platform_descriptor.minOverdriveVDDC = in init_overdrive_limits_V1_4()
968 hwmgr->platform_descriptor.maxOverdriveVDDC = in init_overdrive_limits_V1_4()
971 hwmgr->platform_descriptor.overdriveVDDCStep = 0; in init_overdrive_limits_V1_4()
975 static int init_overdrive_limits_V2_1(struct pp_hwmgr *hwmgr, in init_overdrive_limits_V2_1() argument
994 hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock); in init_overdrive_limits_V2_1()
995 hwmgr->platform_descriptor.overdriveLimit.memoryClock = le32_to_cpu(header->ulMaxMemoryClock); in init_overdrive_limits_V2_1()
998 hwmgr->platform_descriptor.minOverdriveVDDC = 0; in init_overdrive_limits_V2_1()
999 hwmgr->platform_descriptor.maxOverdriveVDDC = 0; in init_overdrive_limits_V2_1()
1000 hwmgr->platform_descriptor.overdriveVDDCStep = 0; in init_overdrive_limits_V2_1()
1005 static int init_overdrive_limits(struct pp_hwmgr *hwmgr, in init_overdrive_limits() argument
1014 hwmgr->platform_descriptor.overdriveLimit.engineClock = 0; in init_overdrive_limits()
1015 hwmgr->platform_descriptor.overdriveLimit.memoryClock = 0; in init_overdrive_limits()
1016 hwmgr->platform_descriptor.minOverdriveVDDC = 0; in init_overdrive_limits()
1017 hwmgr->platform_descriptor.maxOverdriveVDDC = 0; in init_overdrive_limits()
1020 fw_info = cgs_atom_get_data_table(hwmgr->device, in init_overdrive_limits()
1026 result = init_overdrive_limits_V1_4(hwmgr, in init_overdrive_limits()
1032 result = init_overdrive_limits_V2_1(hwmgr, in init_overdrive_limits()
1036 if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 in init_overdrive_limits()
1037 && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0 in init_overdrive_limits()
1038 && !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in init_overdrive_limits()
1040 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in init_overdrive_limits()
1046 static int get_uvd_clock_voltage_limit_table(struct pp_hwmgr *hwmgr, in get_uvd_clock_voltage_limit_table() argument
1079 static int get_vce_clock_voltage_limit_table(struct pp_hwmgr *hwmgr, in get_vce_clock_voltage_limit_table() argument
1111 static int get_samu_clock_voltage_limit_table(struct pp_hwmgr *hwmgr, in get_samu_clock_voltage_limit_table() argument
1139 static int get_acp_clock_voltage_limit_table(struct pp_hwmgr *hwmgr, in get_acp_clock_voltage_limit_table() argument
1167 static int init_clock_voltage_dependency(struct pp_hwmgr *hwmgr, in init_clock_voltage_dependency() argument
1178 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1179 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1180 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1181 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in init_clock_voltage_dependency()
1182 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1183 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1184 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1185 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1186 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1187 hwmgr->dyn_state.ppm_parameter_table = NULL; in init_clock_voltage_dependency()
1188 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1191 hwmgr, powerplay_table); in init_clock_voltage_dependency()
1192 table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, in init_clock_voltage_dependency()
1201 result = get_vce_clock_voltage_limit_table(hwmgr, in init_clock_voltage_dependency()
1202 &hwmgr->dyn_state.vce_clock_voltage_dependency_table, in init_clock_voltage_dependency()
1206 uvd_clock_info_array_offset = get_uvd_clock_info_array_offset(hwmgr, powerplay_table); in init_clock_voltage_dependency()
1207 table_offset = get_uvd_clock_voltage_limit_table_offset(hwmgr, powerplay_table); in init_clock_voltage_dependency()
1216 result = get_uvd_clock_voltage_limit_table(hwmgr, in init_clock_voltage_dependency()
1217 &hwmgr->dyn_state.uvd_clock_voltage_dependency_table, ptable, array); in init_clock_voltage_dependency()
1220 table_offset = get_samu_clock_voltage_limit_table_offset(hwmgr, in init_clock_voltage_dependency()
1227 result = get_samu_clock_voltage_limit_table(hwmgr, in init_clock_voltage_dependency()
1228 &hwmgr->dyn_state.samu_clock_voltage_dependency_table, ptable); in init_clock_voltage_dependency()
1231 table_offset = get_acp_clock_voltage_limit_table_offset(hwmgr, in init_clock_voltage_dependency()
1238 result = get_acp_clock_voltage_limit_table(hwmgr, in init_clock_voltage_dependency()
1239 &hwmgr->dyn_state.acp_clock_voltage_dependency_table, ptable); in init_clock_voltage_dependency()
1242 table_offset = get_cacp_tdp_table_offset(hwmgr, powerplay_table); in init_clock_voltage_dependency()
1250 result = get_cac_tdp_table(hwmgr, &hwmgr->dyn_state.cac_dtp_table, in init_clock_voltage_dependency()
1253 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = in init_clock_voltage_dependency()
1259 result = get_cac_tdp_table(hwmgr, in init_clock_voltage_dependency()
1260 &hwmgr->dyn_state.cac_dtp_table, in init_clock_voltage_dependency()
1273 result = get_clock_voltage_dependency_table(hwmgr, in init_clock_voltage_dependency()
1274 &hwmgr->dyn_state.vddc_dependency_on_sclk, table); in init_clock_voltage_dependency()
1281 result = get_clock_voltage_dependency_table(hwmgr, in init_clock_voltage_dependency()
1282 &hwmgr->dyn_state.vddci_dependency_on_mclk, table); in init_clock_voltage_dependency()
1289 result = get_clock_voltage_dependency_table(hwmgr, in init_clock_voltage_dependency()
1290 &hwmgr->dyn_state.vddc_dependency_on_mclk, table); in init_clock_voltage_dependency()
1297 result = get_clock_voltage_limit(hwmgr, in init_clock_voltage_dependency()
1298 &hwmgr->dyn_state.max_clock_voltage_on_dc, limit_table); in init_clock_voltage_dependency()
1301 if (result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) && in init_clock_voltage_dependency()
1302 (0 != hwmgr->dyn_state.vddc_dependency_on_mclk->count)) in init_clock_voltage_dependency()
1303 result = get_valid_clk(hwmgr, &hwmgr->dyn_state.valid_mclk_values, in init_clock_voltage_dependency()
1304 hwmgr->dyn_state.vddc_dependency_on_mclk); in init_clock_voltage_dependency()
1306 if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) && in init_clock_voltage_dependency()
1307 (0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count)) in init_clock_voltage_dependency()
1308 result = get_valid_clk(hwmgr, in init_clock_voltage_dependency()
1309 &hwmgr->dyn_state.valid_sclk_values, in init_clock_voltage_dependency()
1310 hwmgr->dyn_state.vddc_dependency_on_sclk); in init_clock_voltage_dependency()
1316 result = get_clock_voltage_dependency_table(hwmgr, in init_clock_voltage_dependency()
1317 &hwmgr->dyn_state.mvdd_dependency_on_mclk, table); in init_clock_voltage_dependency()
1321 table_offset = get_sclk_vdd_gfx_clock_voltage_dependency_table_offset(hwmgr, in init_clock_voltage_dependency()
1327 result = get_clock_voltage_dependency_table(hwmgr, in init_clock_voltage_dependency()
1328 &hwmgr->dyn_state.vdd_gfx_dependency_on_sclk, table); in init_clock_voltage_dependency()
1334 static int get_cac_leakage_table(struct pp_hwmgr *hwmgr, in get_cac_leakage_table() argument
1341 if (hwmgr == NULL || table == NULL || ptable == NULL) in get_cac_leakage_table()
1355 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in get_cac_leakage_table()
1371 static int get_platform_power_management_table(struct pp_hwmgr *hwmgr, in get_platform_power_management_table() argument
1389 hwmgr->dyn_state.ppm_parameter_table = ptr; in get_platform_power_management_table()
1394 static int init_dpm2_parameters(struct pp_hwmgr *hwmgr, in init_dpm2_parameters() argument
1413 hwmgr->platform_descriptor.TDPLimit = le32_to_cpu(ptable5->ulTDPLimit); in init_dpm2_parameters()
1414 hwmgr->platform_descriptor.nearTDPLimit = le32_to_cpu(ptable5->ulNearTDPLimit); in init_dpm2_parameters()
1416 hwmgr->platform_descriptor.TDPODLimit = le16_to_cpu(ptable5->usTDPODLimit); in init_dpm2_parameters()
1417 hwmgr->platform_descriptor.TDPAdjustment = 0; in init_dpm2_parameters()
1419 hwmgr->platform_descriptor.VidAdjustment = 0; in init_dpm2_parameters()
1420 hwmgr->platform_descriptor.VidAdjustmentPolarity = 0; in init_dpm2_parameters()
1421 hwmgr->platform_descriptor.VidMinLimit = 0; in init_dpm2_parameters()
1422 hwmgr->platform_descriptor.VidMaxLimit = 1500000; in init_dpm2_parameters()
1423 hwmgr->platform_descriptor.VidStep = 6250; in init_dpm2_parameters()
1425 hwmgr->platform_descriptor.nearTDPLimitAdjusted = le32_to_cpu(ptable5->ulNearTDPLimit); in init_dpm2_parameters()
1427 if (hwmgr->platform_descriptor.TDPODLimit != 0) in init_dpm2_parameters()
1428 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in init_dpm2_parameters()
1431 hwmgr->platform_descriptor.SQRampingThreshold = le32_to_cpu(ptable5->ulSQRampingThreshold); in init_dpm2_parameters()
1433 hwmgr->platform_descriptor.CACLeakage = le32_to_cpu(ptable5->ulCACLeakage); in init_dpm2_parameters()
1435 hwmgr->dyn_state.cac_leakage_table = NULL; in init_dpm2_parameters()
1441 result = get_cac_leakage_table(hwmgr, in init_dpm2_parameters()
1442 &hwmgr->dyn_state.cac_leakage_table, pCAC_leakage_table); in init_dpm2_parameters()
1445 hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(ptable5->usLoadLineSlope); in init_dpm2_parameters()
1447 hwmgr->dyn_state.ppm_parameter_table = NULL; in init_dpm2_parameters()
1459 if (0 == get_platform_power_management_table(hwmgr, atom_ppm_table)) in init_dpm2_parameters()
1460 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in init_dpm2_parameters()
1468 static int init_phase_shedding_table(struct pp_hwmgr *hwmgr, in init_phase_shedding_table() argument
1503 hwmgr->dyn_state.vddc_phase_shed_limits_table = table; in init_phase_shedding_table()
1511 struct pp_hwmgr *hwmgr) in get_number_of_vce_state_table_entries() argument
1514 get_powerplay_table(hwmgr); in get_number_of_vce_state_table_entries()
1516 get_vce_state_table(hwmgr, table); in get_number_of_vce_state_table_entries()
1524 int get_vce_state_table_entry(struct pp_hwmgr *hwmgr, in get_vce_state_table_entry() argument
1530 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr); in get_vce_state_table_entry()
1532 const ATOM_PPLIB_VCE_State_Table *vce_state_table = get_vce_state_table(hwmgr, powerplay_table); in get_vce_state_table_entry()
1534 …unsigned short vce_clock_info_array_offset = get_vce_clock_info_array_offset(hwmgr, powerplay_tabl… in get_vce_state_table_entry()
1557 static int pp_tables_initialize(struct pp_hwmgr *hwmgr) in pp_tables_initialize() argument
1562 hwmgr->need_pp_table_upload = true; in pp_tables_initialize()
1564 powerplay_table = get_powerplay_table(hwmgr); in pp_tables_initialize()
1566 result = init_powerplay_tables(hwmgr, powerplay_table); in pp_tables_initialize()
1571 result = set_platform_caps(hwmgr, in pp_tables_initialize()
1577 result = init_thermal_controller(hwmgr, powerplay_table); in pp_tables_initialize()
1582 result = init_overdrive_limits(hwmgr, powerplay_table); in pp_tables_initialize()
1587 result = init_clock_voltage_dependency(hwmgr, in pp_tables_initialize()
1593 result = init_dpm2_parameters(hwmgr, powerplay_table); in pp_tables_initialize()
1598 result = init_phase_shedding_table(hwmgr, powerplay_table); in pp_tables_initialize()
1606 static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr) in pp_tables_uninitialize() argument
1608 if (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) { in pp_tables_uninitialize()
1609 kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); in pp_tables_uninitialize()
1610 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in pp_tables_uninitialize()
1613 if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) { in pp_tables_uninitialize()
1614 kfree(hwmgr->dyn_state.vddci_dependency_on_mclk); in pp_tables_uninitialize()
1615 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; in pp_tables_uninitialize()
1618 if (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) { in pp_tables_uninitialize()
1619 kfree(hwmgr->dyn_state.vddc_dependency_on_mclk); in pp_tables_uninitialize()
1620 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; in pp_tables_uninitialize()
1623 if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) { in pp_tables_uninitialize()
1624 kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk); in pp_tables_uninitialize()
1625 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; in pp_tables_uninitialize()
1628 if (NULL != hwmgr->dyn_state.valid_mclk_values) { in pp_tables_uninitialize()
1629 kfree(hwmgr->dyn_state.valid_mclk_values); in pp_tables_uninitialize()
1630 hwmgr->dyn_state.valid_mclk_values = NULL; in pp_tables_uninitialize()
1633 if (NULL != hwmgr->dyn_state.valid_sclk_values) { in pp_tables_uninitialize()
1634 kfree(hwmgr->dyn_state.valid_sclk_values); in pp_tables_uninitialize()
1635 hwmgr->dyn_state.valid_sclk_values = NULL; in pp_tables_uninitialize()
1638 if (NULL != hwmgr->dyn_state.cac_leakage_table) { in pp_tables_uninitialize()
1639 kfree(hwmgr->dyn_state.cac_leakage_table); in pp_tables_uninitialize()
1640 hwmgr->dyn_state.cac_leakage_table = NULL; in pp_tables_uninitialize()
1643 if (NULL != hwmgr->dyn_state.vddc_phase_shed_limits_table) { in pp_tables_uninitialize()
1644 kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table); in pp_tables_uninitialize()
1645 hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL; in pp_tables_uninitialize()
1648 if (NULL != hwmgr->dyn_state.vce_clock_voltage_dependency_table) { in pp_tables_uninitialize()
1649 kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table); in pp_tables_uninitialize()
1650 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1653 if (NULL != hwmgr->dyn_state.uvd_clock_voltage_dependency_table) { in pp_tables_uninitialize()
1654 kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table); in pp_tables_uninitialize()
1655 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1658 if (NULL != hwmgr->dyn_state.samu_clock_voltage_dependency_table) { in pp_tables_uninitialize()
1659 kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table); in pp_tables_uninitialize()
1660 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1663 if (NULL != hwmgr->dyn_state.acp_clock_voltage_dependency_table) { in pp_tables_uninitialize()
1664 kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table); in pp_tables_uninitialize()
1665 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1668 if (NULL != hwmgr->dyn_state.cac_dtp_table) { in pp_tables_uninitialize()
1669 kfree(hwmgr->dyn_state.cac_dtp_table); in pp_tables_uninitialize()
1670 hwmgr->dyn_state.cac_dtp_table = NULL; in pp_tables_uninitialize()
1673 if (NULL != hwmgr->dyn_state.ppm_parameter_table) { in pp_tables_uninitialize()
1674 kfree(hwmgr->dyn_state.ppm_parameter_table); in pp_tables_uninitialize()
1675 hwmgr->dyn_state.ppm_parameter_table = NULL; in pp_tables_uninitialize()
1678 if (NULL != hwmgr->dyn_state.vdd_gfx_dependency_on_sclk) { in pp_tables_uninitialize()
1679 kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk); in pp_tables_uninitialize()
1680 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; in pp_tables_uninitialize()
1683 if (NULL != hwmgr->dyn_state.vq_budgeting_table) { in pp_tables_uninitialize()
1684 kfree(hwmgr->dyn_state.vq_budgeting_table); in pp_tables_uninitialize()
1685 hwmgr->dyn_state.vq_budgeting_table = NULL; in pp_tables_uninitialize()