Lines Matching refs:hwmgr
118 int smu7_get_mc_microcode_version (struct pp_hwmgr *hwmgr) in smu7_get_mc_microcode_version() argument
120 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); in smu7_get_mc_microcode_version()
122 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); in smu7_get_mc_microcode_version()
127 uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) in smu7_get_current_pcie_speed() argument
132 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_speed()
138 int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) in smu7_get_current_pcie_lane_number() argument
143 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_lane_number()
158 int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) in smu7_enable_smc_voltage_controller() argument
160 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK) in smu7_enable_smc_voltage_controller()
161 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable); in smu7_enable_smc_voltage_controller()
171 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr) in smu7_voltage_control() argument
174 (const struct smu7_hwmgr *)(hwmgr->backend); in smu7_voltage_control()
185 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr) in smu7_enable_voltage_control() argument
188 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_enable_voltage_control()
223 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr) in smu7_construct_voltage_tables() argument
225 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_construct_voltage_tables()
227 (struct phm_ppt_v1_information *)hwmgr->pptable; in smu7_construct_voltage_tables()
232 result = atomctrl_get_voltage_table_v3(hwmgr, in smu7_construct_voltage_tables()
239 if (hwmgr->pp_table_version == PP_TABLE_V1) in smu7_construct_voltage_tables()
242 else if (hwmgr->pp_table_version == PP_TABLE_V0) in smu7_construct_voltage_tables()
244 hwmgr->dyn_state.mvdd_dependency_on_mclk); in smu7_construct_voltage_tables()
252 result = atomctrl_get_voltage_table_v3(hwmgr, in smu7_construct_voltage_tables()
259 if (hwmgr->pp_table_version == PP_TABLE_V1) in smu7_construct_voltage_tables()
262 else if (hwmgr->pp_table_version == PP_TABLE_V0) in smu7_construct_voltage_tables()
264 hwmgr->dyn_state.vddci_dependency_on_mclk); in smu7_construct_voltage_tables()
280 result = atomctrl_get_voltage_table_v3(hwmgr, in smu7_construct_voltage_tables()
287 if (hwmgr->pp_table_version == PP_TABLE_V0) in smu7_construct_voltage_tables()
289 hwmgr->dyn_state.vddc_dependency_on_mclk); in smu7_construct_voltage_tables()
290 else if (hwmgr->pp_table_version == PP_TABLE_V1) in smu7_construct_voltage_tables()
298 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDC); in smu7_construct_voltage_tables()
305 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX); in smu7_construct_voltage_tables()
312 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDCI); in smu7_construct_voltage_tables()
319 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_MVDD); in smu7_construct_voltage_tables()
336 struct pp_hwmgr *hwmgr) in smu7_program_static_screen_threshold_parameters() argument
338 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_program_static_screen_threshold_parameters()
341 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_static_screen_threshold_parameters()
345 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_static_screen_threshold_parameters()
358 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr) in smu7_enable_display_gap() argument
361 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_enable_display_gap()
370 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_enable_display_gap()
382 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr) in smu7_program_voting_clients() argument
384 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_program_voting_clients()
387 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_voting_clients()
389 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_voting_clients()
392 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_voting_clients()
394 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_voting_clients()
396 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_voting_clients()
398 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_voting_clients()
400 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_voting_clients()
402 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_voting_clients()
404 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_voting_clients()
406 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_voting_clients()
412 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr) in smu7_clear_voting_clients() argument
415 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_clear_voting_clients()
417 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_clear_voting_clients()
420 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_clear_voting_clients()
422 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_clear_voting_clients()
424 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_clear_voting_clients()
426 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_clear_voting_clients()
428 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_clear_voting_clients()
430 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_clear_voting_clients()
432 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_clear_voting_clients()
434 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_clear_voting_clients()
443 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, in smu7_copy_and_switch_arb_sets() argument
453 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); in smu7_copy_and_switch_arb_sets()
454 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); in smu7_copy_and_switch_arb_sets()
455 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); in smu7_copy_and_switch_arb_sets()
458 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); in smu7_copy_and_switch_arb_sets()
459 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); in smu7_copy_and_switch_arb_sets()
460 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); in smu7_copy_and_switch_arb_sets()
468 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); in smu7_copy_and_switch_arb_sets()
469 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); in smu7_copy_and_switch_arb_sets()
470 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); in smu7_copy_and_switch_arb_sets()
473 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); in smu7_copy_and_switch_arb_sets()
474 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); in smu7_copy_and_switch_arb_sets()
475 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); in smu7_copy_and_switch_arb_sets()
481 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); in smu7_copy_and_switch_arb_sets()
483 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); in smu7_copy_and_switch_arb_sets()
484 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest); in smu7_copy_and_switch_arb_sets()
489 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr) in smu7_reset_to_default() argument
491 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults); in smu7_reset_to_default()
501 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) in smu7_initial_switch_from_arbf0_to_f1() argument
503 return smu7_copy_and_switch_arb_sets(hwmgr, in smu7_initial_switch_from_arbf0_to_f1()
507 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr) in smu7_force_switch_to_arbf0() argument
511 tmp = (cgs_read_ind_register(hwmgr->device, in smu7_force_switch_to_arbf0()
518 return smu7_copy_and_switch_arb_sets(hwmgr, in smu7_force_switch_to_arbf0()
522 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) in smu7_setup_default_pcie_table() argument
524 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_setup_default_pcie_table()
527 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_setup_default_pcie_table()
549 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_LINK); in smu7_setup_default_pcie_table()
568 smum_update_smc_table(hwmgr, SMU_BIF_TABLE); in smu7_setup_default_pcie_table()
615 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr) in smu7_reset_dpm_tables() argument
617 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_reset_dpm_tables()
623 smum_get_mac_definition(hwmgr->smumgr, in smu7_reset_dpm_tables()
628 smum_get_mac_definition(hwmgr->smumgr, in smu7_reset_dpm_tables()
633 smum_get_mac_definition(hwmgr->smumgr, in smu7_reset_dpm_tables()
638 smum_get_mac_definition(hwmgr->smumgr, in smu7_reset_dpm_tables()
643 smum_get_mac_definition(hwmgr->smumgr, in smu7_reset_dpm_tables()
657 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr) in smu7_setup_dpm_tables_v0() argument
659 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_setup_dpm_tables_v0()
661 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_setup_dpm_tables_v0()
663 hwmgr->dyn_state.vddc_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
665 hwmgr->dyn_state.cac_leakage_table; in smu7_setup_dpm_tables_v0()
715 allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
726 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
743 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr) in smu7_setup_dpm_tables_v1() argument
745 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_setup_dpm_tables_v1()
747 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_setup_dpm_tables_v1()
805 int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) in smu7_setup_default_dpm_tables() argument
807 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_setup_default_dpm_tables()
809 smu7_reset_dpm_tables(hwmgr); in smu7_setup_default_dpm_tables()
811 if (hwmgr->pp_table_version == PP_TABLE_V1) in smu7_setup_default_dpm_tables()
812 smu7_setup_dpm_tables_v1(hwmgr); in smu7_setup_default_dpm_tables()
813 else if (hwmgr->pp_table_version == PP_TABLE_V0) in smu7_setup_default_dpm_tables()
814 smu7_setup_dpm_tables_v0(hwmgr); in smu7_setup_default_dpm_tables()
816 smu7_setup_default_pcie_table(hwmgr); in smu7_setup_default_dpm_tables()
824 uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr) in smu7_get_xclk() argument
832 …tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_… in smu7_get_xclk()
837 cgs_get_active_displays_info(hwmgr->device, &info); in smu7_get_xclk()
840 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE); in smu7_get_xclk()
848 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) in smu7_enable_vrhot_gpio_interrupt() argument
851 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_enable_vrhot_gpio_interrupt()
853 return smum_send_msg_to_smc(hwmgr->smumgr, in smu7_enable_vrhot_gpio_interrupt()
859 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr) in smu7_enable_sclk_control() argument
861 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, in smu7_enable_sclk_control()
866 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr) in smu7_enable_ulv() argument
868 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_enable_ulv()
871 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV); in smu7_enable_ulv()
876 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr) in smu7_disable_ulv() argument
878 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_disable_ulv()
881 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV); in smu7_disable_ulv()
886 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) in smu7_enable_deep_sleep_master_switch() argument
888 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_enable_deep_sleep_master_switch()
890 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON)) in smu7_enable_deep_sleep_master_switch()
895 if (smum_send_msg_to_smc(hwmgr->smumgr, in smu7_enable_deep_sleep_master_switch()
906 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) in smu7_disable_deep_sleep_master_switch() argument
908 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_disable_deep_sleep_master_switch()
910 if (smum_send_msg_to_smc(hwmgr->smumgr, in smu7_disable_deep_sleep_master_switch()
921 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr) in smu7_disable_handshake_uvd() argument
923 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_disable_handshake_uvd()
926 + smum_get_offsetof(hwmgr->smumgr, in smu7_disable_handshake_uvd()
929 soft_register_value = cgs_read_ind_register(hwmgr->device, in smu7_disable_handshake_uvd()
931 soft_register_value |= smum_get_mac_definition(hwmgr->smumgr, in smu7_disable_handshake_uvd()
933 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_disable_handshake_uvd()
938 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) in smu7_enable_sclk_mclk_dpm() argument
940 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_enable_sclk_mclk_dpm()
945 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)), in smu7_enable_sclk_mclk_dpm()
951 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK)) in smu7_enable_sclk_mclk_dpm()
952 smu7_disable_handshake_uvd(hwmgr); in smu7_enable_sclk_mclk_dpm()
954 (0 == smum_send_msg_to_smc(hwmgr->smumgr, in smu7_enable_sclk_mclk_dpm()
959 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); in smu7_enable_sclk_mclk_dpm()
961 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5); in smu7_enable_sclk_mclk_dpm()
962 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5); in smu7_enable_sclk_mclk_dpm()
963 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005); in smu7_enable_sclk_mclk_dpm()
965 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005); in smu7_enable_sclk_mclk_dpm()
966 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005); in smu7_enable_sclk_mclk_dpm()
967 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005); in smu7_enable_sclk_mclk_dpm()
973 static int smu7_start_dpm(struct pp_hwmgr *hwmgr) in smu7_start_dpm() argument
975 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_start_dpm()
979 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, in smu7_start_dpm()
984 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, in smu7_start_dpm()
989 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_start_dpm()
991 smum_get_offsetof(hwmgr->smumgr, SMU_SoftRegisters, in smu7_start_dpm()
993 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, in smu7_start_dpm()
997 (0 == smum_send_msg_to_smc(hwmgr->smumgr, in smu7_start_dpm()
1003 if (smu7_enable_sclk_mclk_dpm(hwmgr)) { in smu7_start_dpm()
1011 (0 == smum_send_msg_to_smc(hwmgr->smumgr, in smu7_start_dpm()
1017 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_start_dpm()
1019 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr, in smu7_start_dpm()
1028 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) in smu7_disable_sclk_mclk_dpm() argument
1030 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_disable_sclk_mclk_dpm()
1034 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), in smu7_disable_sclk_mclk_dpm()
1037 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Disable); in smu7_disable_sclk_mclk_dpm()
1042 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), in smu7_disable_sclk_mclk_dpm()
1045 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_Disable); in smu7_disable_sclk_mclk_dpm()
1051 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr) in smu7_stop_dpm() argument
1053 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_stop_dpm()
1056 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, in smu7_stop_dpm()
1059 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, in smu7_stop_dpm()
1065 (smum_send_msg_to_smc(hwmgr->smumgr, in smu7_stop_dpm()
1071 smu7_disable_sclk_mclk_dpm(hwmgr); in smu7_stop_dpm()
1073 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), in smu7_stop_dpm()
1077 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Disable); in smu7_stop_dpm()
1082 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) in smu7_set_dpm_event_sources() argument
1111 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL, in smu7_set_dpm_event_sources()
1113 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, in smu7_set_dpm_event_sources()
1115 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_set_dpm_event_sources()
1118 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, in smu7_set_dpm_event_sources()
1122 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, in smu7_enable_auto_throttle_source() argument
1125 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_enable_auto_throttle_source()
1129 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); in smu7_enable_auto_throttle_source()
1134 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) in smu7_enable_thermal_auto_throttle() argument
1136 return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); in smu7_enable_thermal_auto_throttle()
1139 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr, in smu7_disable_auto_throttle_source() argument
1142 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_disable_auto_throttle_source()
1146 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); in smu7_disable_auto_throttle_source()
1151 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) in smu7_disable_thermal_auto_throttle() argument
1153 return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); in smu7_disable_thermal_auto_throttle()
1156 int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr) in smu7_pcie_performance_request() argument
1158 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_pcie_performance_request()
1164 int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) in smu7_enable_dpm_tasks() argument
1169 tmp_result = (!smum_is_dpm_running(hwmgr)) ? 0 : -1; in smu7_enable_dpm_tasks()
1174 if (smu7_voltage_control(hwmgr)) { in smu7_enable_dpm_tasks()
1175 tmp_result = smu7_enable_voltage_control(hwmgr); in smu7_enable_dpm_tasks()
1180 tmp_result = smu7_construct_voltage_tables(hwmgr); in smu7_enable_dpm_tasks()
1185 smum_initialize_mc_reg_table(hwmgr); in smu7_enable_dpm_tasks()
1187 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_enable_dpm_tasks()
1189 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_enable_dpm_tasks()
1192 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_enable_dpm_tasks()
1194 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_enable_dpm_tasks()
1197 tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr); in smu7_enable_dpm_tasks()
1202 tmp_result = smu7_enable_display_gap(hwmgr); in smu7_enable_dpm_tasks()
1206 tmp_result = smu7_program_voting_clients(hwmgr); in smu7_enable_dpm_tasks()
1210 tmp_result = smum_process_firmware_header(hwmgr); in smu7_enable_dpm_tasks()
1214 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr); in smu7_enable_dpm_tasks()
1219 result = smu7_setup_default_dpm_tables(hwmgr); in smu7_enable_dpm_tasks()
1223 tmp_result = smum_init_smc_table(hwmgr); in smu7_enable_dpm_tasks()
1227 tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr); in smu7_enable_dpm_tasks()
1231 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_NoDisplay); in smu7_enable_dpm_tasks()
1233 tmp_result = smu7_enable_sclk_control(hwmgr); in smu7_enable_dpm_tasks()
1237 tmp_result = smu7_enable_smc_voltage_controller(hwmgr); in smu7_enable_dpm_tasks()
1241 tmp_result = smu7_enable_ulv(hwmgr); in smu7_enable_dpm_tasks()
1245 tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr); in smu7_enable_dpm_tasks()
1249 tmp_result = smu7_enable_didt_config(hwmgr); in smu7_enable_dpm_tasks()
1253 tmp_result = smu7_start_dpm(hwmgr); in smu7_enable_dpm_tasks()
1257 tmp_result = smu7_enable_smc_cac(hwmgr); in smu7_enable_dpm_tasks()
1261 tmp_result = smu7_enable_power_containment(hwmgr); in smu7_enable_dpm_tasks()
1265 tmp_result = smu7_power_control_set_level(hwmgr); in smu7_enable_dpm_tasks()
1269 tmp_result = smu7_enable_thermal_auto_throttle(hwmgr); in smu7_enable_dpm_tasks()
1273 tmp_result = smu7_pcie_performance_request(hwmgr); in smu7_enable_dpm_tasks()
1280 int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr) in smu7_disable_dpm_tasks() argument
1284 tmp_result = (smum_is_dpm_running(hwmgr)) ? 0 : -1; in smu7_disable_dpm_tasks()
1289 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_disable_dpm_tasks()
1291 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_disable_dpm_tasks()
1294 tmp_result = smu7_disable_power_containment(hwmgr); in smu7_disable_dpm_tasks()
1298 tmp_result = smu7_disable_smc_cac(hwmgr); in smu7_disable_dpm_tasks()
1302 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_disable_dpm_tasks()
1304 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_disable_dpm_tasks()
1307 tmp_result = smu7_disable_thermal_auto_throttle(hwmgr); in smu7_disable_dpm_tasks()
1311 if (1 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) { in smu7_disable_dpm_tasks()
1312 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableAvfs)), in smu7_disable_dpm_tasks()
1317 tmp_result = smu7_stop_dpm(hwmgr); in smu7_disable_dpm_tasks()
1321 tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr); in smu7_disable_dpm_tasks()
1325 tmp_result = smu7_disable_ulv(hwmgr); in smu7_disable_dpm_tasks()
1329 tmp_result = smu7_clear_voting_clients(hwmgr); in smu7_disable_dpm_tasks()
1333 tmp_result = smu7_reset_to_default(hwmgr); in smu7_disable_dpm_tasks()
1337 tmp_result = smu7_force_switch_to_arbf0(hwmgr); in smu7_disable_dpm_tasks()
1344 int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr) in smu7_reset_asic_tasks() argument
1350 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) in smu7_init_dpm_defaults() argument
1352 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_init_dpm_defaults()
1354 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_init_dpm_defaults()
1371 data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; in smu7_init_dpm_defaults()
1372 data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; in smu7_init_dpm_defaults()
1373 data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; in smu7_init_dpm_defaults()
1381 data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false; in smu7_init_dpm_defaults()
1384 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, in smu7_init_dpm_defaults()
1388 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_init_dpm_defaults()
1390 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, in smu7_init_dpm_defaults()
1396 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_init_dpm_defaults()
1398 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, in smu7_init_dpm_defaults()
1401 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, in smu7_init_dpm_defaults()
1407 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu7_init_dpm_defaults()
1411 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_init_dpm_defaults()
1413 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, in smu7_init_dpm_defaults()
1416 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, in smu7_init_dpm_defaults()
1422 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu7_init_dpm_defaults()
1426 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu7_init_dpm_defaults()
1429 if ((hwmgr->pp_table_version != PP_TABLE_V0) in smu7_init_dpm_defaults()
1431 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu7_init_dpm_defaults()
1450 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) in smu7_get_evv_voltages() argument
1452 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_get_evv_voltages()
1459 (struct phm_ppt_v1_information *)hwmgr->pptable; in smu7_get_evv_voltages()
1467 if ((hwmgr->pp_table_version == PP_TABLE_V1) in smu7_get_evv_voltages()
1468 && !phm_get_sclk_for_voltage_evv(hwmgr, in smu7_get_evv_voltages()
1470 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_get_evv_voltages()
1483 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk, in smu7_get_evv_voltages()
1499 if ((hwmgr->pp_table_version == PP_TABLE_V0) in smu7_get_evv_voltages()
1500 || !phm_get_sclk_for_voltage_evv(hwmgr, in smu7_get_evv_voltages()
1502 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_get_evv_voltages()
1517 if (phm_get_voltage_evv_on_sclk(hwmgr, in smu7_get_evv_voltages()
1547 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr, in smu7_patch_ppt_v1_with_vdd_leakage() argument
1574 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, in smu7_patch_lookup_table_with_leakage() argument
1581 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, in smu7_patch_lookup_table_with_leakage()
1588 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table, in smu7_patch_clock_voltage_limits_with_vddc_leakage() argument
1592 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_patch_clock_voltage_limits_with_vddc_leakage()
1593 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); in smu7_patch_clock_voltage_limits_with_vddc_leakage()
1594 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in smu7_patch_clock_voltage_limits_with_vddc_leakage()
1600 struct pp_hwmgr *hwmgr) in smu7_patch_voltage_dependency_tables_with_lookup_table() argument
1604 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_patch_voltage_dependency_tables_with_lookup_table()
1606 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_patch_voltage_dependency_tables_with_lookup_table()
1645 static int phm_add_voltage(struct pp_hwmgr *hwmgr, in phm_add_voltage() argument
1656 i = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX); in phm_add_voltage()
1682 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) in smu7_calc_voltage_dependency_tables() argument
1686 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_calc_voltage_dependency_tables()
1687 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_calc_voltage_dependency_tables()
1705 phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record); in smu7_calc_voltage_dependency_tables()
1718 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); in smu7_calc_voltage_dependency_tables()
1724 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) in smu7_calc_mm_voltage_dependency_table() argument
1728 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_calc_mm_voltage_dependency_table()
1729 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_calc_mm_voltage_dependency_table()
1744 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); in smu7_calc_mm_voltage_dependency_table()
1750 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr, in smu7_sort_lookup_table() argument
1775 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr) in smu7_complete_dependency_tables() argument
1779 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_complete_dependency_tables()
1781 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_complete_dependency_tables()
1784 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr, in smu7_complete_dependency_tables()
1789 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, in smu7_complete_dependency_tables()
1793 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr, in smu7_complete_dependency_tables()
1798 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, in smu7_complete_dependency_tables()
1804 tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr); in smu7_complete_dependency_tables()
1808 tmp_result = smu7_calc_voltage_dependency_tables(hwmgr); in smu7_complete_dependency_tables()
1812 tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr); in smu7_complete_dependency_tables()
1816 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table); in smu7_complete_dependency_tables()
1820 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); in smu7_complete_dependency_tables()
1827 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr) in smu7_set_private_data_based_on_pptable_v1() argument
1830 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_set_private_data_based_on_pptable_v1()
1860 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk; in smu7_set_private_data_based_on_pptable_v1()
1861 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk; in smu7_set_private_data_based_on_pptable_v1()
1862 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc; in smu7_set_private_data_based_on_pptable_v1()
1863 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci; in smu7_set_private_data_based_on_pptable_v1()
1868 int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr) in smu7_patch_voltage_workaround() argument
1871 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_patch_voltage_workaround()
1887 cgs_query_system_info(hwmgr->device, &sys_info); in smu7_patch_voltage_workaround()
1891 cgs_query_system_info(hwmgr->device, &sys_info); in smu7_patch_voltage_workaround()
1895 cgs_query_system_info(hwmgr->device, &sys_info); in smu7_patch_voltage_workaround()
1898 if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 && in smu7_patch_voltage_workaround()
1915 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr) in smu7_thermal_parameter_init() argument
1920 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_thermal_parameter_init()
1923 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) { in smu7_thermal_parameter_init()
1924 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); in smu7_thermal_parameter_init()
1947 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg); in smu7_thermal_parameter_init()
1954 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) { in smu7_thermal_parameter_init()
1955 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit = in smu7_thermal_parameter_init()
1956 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; in smu7_thermal_parameter_init()
1958 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit = in smu7_thermal_parameter_init()
1959 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; in smu7_thermal_parameter_init()
1961 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1; in smu7_thermal_parameter_init()
1963 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100; in smu7_thermal_parameter_init()
1965 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit = in smu7_thermal_parameter_init()
1966 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; in smu7_thermal_parameter_init()
1968 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1; in smu7_thermal_parameter_init()
1977 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = in smu7_thermal_parameter_init()
1978 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; in smu7_thermal_parameter_init()
1980 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = in smu7_thermal_parameter_init()
1981 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM; in smu7_thermal_parameter_init()
1983 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit = in smu7_thermal_parameter_init()
1986 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit = in smu7_thermal_parameter_init()
1989 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = in smu7_thermal_parameter_init()
1992 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep = in smu7_thermal_parameter_init()
1995 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp = in smu7_thermal_parameter_init()
1997 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu7_thermal_parameter_init()
2011 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr, in smu7_patch_ppt_v0_with_vdd_leakage() argument
2031 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr, in smu7_patch_vddc() argument
2035 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_patch_vddc()
2039 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, in smu7_patch_vddc()
2045 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr, in smu7_patch_vddci() argument
2049 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_patch_vddci()
2053 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, in smu7_patch_vddci()
2059 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr, in smu7_patch_vce_vddc() argument
2063 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_patch_vce_vddc()
2067 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, in smu7_patch_vce_vddc()
2074 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr, in smu7_patch_uvd_vddc() argument
2078 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_patch_uvd_vddc()
2082 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, in smu7_patch_uvd_vddc()
2088 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr, in smu7_patch_vddc_shed_limit() argument
2092 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_patch_vddc_shed_limit()
2096 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage, in smu7_patch_vddc_shed_limit()
2102 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr, in smu7_patch_samu_vddc() argument
2106 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_patch_samu_vddc()
2110 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, in smu7_patch_samu_vddc()
2116 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr, in smu7_patch_acp_vddc() argument
2120 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_patch_acp_vddc()
2124 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, in smu7_patch_acp_vddc()
2130 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr, in smu7_patch_limits_vddc() argument
2134 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_patch_limits_vddc()
2138 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, in smu7_patch_limits_vddc()
2142 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci, in smu7_patch_limits_vddc()
2150 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab) in smu7_patch_cac_vddc() argument
2154 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_patch_cac_vddc()
2159 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage); in smu7_patch_cac_vddc()
2167 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr) in smu7_patch_dependency_tables_with_leakage() argument
2171 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk); in smu7_patch_dependency_tables_with_leakage()
2175 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk); in smu7_patch_dependency_tables_with_leakage()
2179 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in smu7_patch_dependency_tables_with_leakage()
2183 tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk); in smu7_patch_dependency_tables_with_leakage()
2187 tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table); in smu7_patch_dependency_tables_with_leakage()
2191 tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table); in smu7_patch_dependency_tables_with_leakage()
2195 tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table); in smu7_patch_dependency_tables_with_leakage()
2199 tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table); in smu7_patch_dependency_tables_with_leakage()
2203 tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table); in smu7_patch_dependency_tables_with_leakage()
2207 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac); in smu7_patch_dependency_tables_with_leakage()
2211 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc); in smu7_patch_dependency_tables_with_leakage()
2215 tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table); in smu7_patch_dependency_tables_with_leakage()
2223 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr) in smu7_set_private_data_based_on_pptable_v0() argument
2225 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_set_private_data_based_on_pptable_v0()
2227 …struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_depende… in smu7_set_private_data_based_on_pptable_v0()
2228 …struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_depende… in smu7_set_private_data_based_on_pptable_v0()
2229 …struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_depen… in smu7_set_private_data_based_on_pptable_v0()
2244 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = in smu7_set_private_data_based_on_pptable_v0()
2246 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = in smu7_set_private_data_based_on_pptable_v0()
2248 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = in smu7_set_private_data_based_on_pptable_v0()
2256 …if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk… in smu7_set_private_data_based_on_pptable_v0()
2257 …hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entrie… in smu7_set_private_data_based_on_pptable_v0()
2262 int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) in smu7_hwmgr_backend_init() argument
2271 hwmgr->backend = data; in smu7_hwmgr_backend_init()
2273 smu7_patch_voltage_workaround(hwmgr); in smu7_hwmgr_backend_init()
2274 smu7_init_dpm_defaults(hwmgr); in smu7_hwmgr_backend_init()
2277 result = smu7_get_evv_voltages(hwmgr); in smu7_hwmgr_backend_init()
2284 if (hwmgr->pp_table_version == PP_TABLE_V1) { in smu7_hwmgr_backend_init()
2285 smu7_complete_dependency_tables(hwmgr); in smu7_hwmgr_backend_init()
2286 smu7_set_private_data_based_on_pptable_v1(hwmgr); in smu7_hwmgr_backend_init()
2287 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { in smu7_hwmgr_backend_init()
2288 smu7_patch_dependency_tables_with_leakage(hwmgr); in smu7_hwmgr_backend_init()
2289 smu7_set_private_data_based_on_pptable_v0(hwmgr); in smu7_hwmgr_backend_init()
2293 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr); in smu7_hwmgr_backend_init()
2300 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = in smu7_hwmgr_backend_init()
2302 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; in smu7_hwmgr_backend_init()
2303 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; in smu7_hwmgr_backend_init()
2307 result = cgs_query_system_info(hwmgr->device, &sys_info); in smu7_hwmgr_backend_init()
2316 result = cgs_query_system_info(hwmgr->device, &sys_info); in smu7_hwmgr_backend_init()
2322 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ in smu7_hwmgr_backend_init()
2324 hwmgr->platform_descriptor.clockStep.engineClock = 500; in smu7_hwmgr_backend_init()
2325 hwmgr->platform_descriptor.clockStep.memoryClock = 500; in smu7_hwmgr_backend_init()
2326 smu7_thermal_parameter_init(hwmgr); in smu7_hwmgr_backend_init()
2329 phm_hwmgr_backend_fini(hwmgr); in smu7_hwmgr_backend_init()
2335 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr) in smu7_force_dpm_highest() argument
2337 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_force_dpm_highest()
2348 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_force_dpm_highest()
2361 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_force_dpm_highest()
2375 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_force_dpm_highest()
2384 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) in smu7_upload_dpm_level_enable_mask() argument
2386 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_upload_dpm_level_enable_mask()
2388 if (hwmgr->pp_table_version == PP_TABLE_V1) in smu7_upload_dpm_level_enable_mask()
2389 phm_apply_dal_min_voltage_request(hwmgr); in smu7_upload_dpm_level_enable_mask()
2394 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_upload_dpm_level_enable_mask()
2401 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_upload_dpm_level_enable_mask()
2409 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr) in smu7_unforce_dpm_levels() argument
2411 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_unforce_dpm_levels()
2413 if (!smum_is_dpm_running(hwmgr)) in smu7_unforce_dpm_levels()
2417 smum_send_msg_to_smc(hwmgr->smumgr, in smu7_unforce_dpm_levels()
2421 return smu7_upload_dpm_level_enable_mask(hwmgr); in smu7_unforce_dpm_levels()
2424 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr) in smu7_force_dpm_lowest() argument
2427 (struct smu7_hwmgr *)(hwmgr->backend); in smu7_force_dpm_lowest()
2432 level = phm_get_lowest_enabled_level(hwmgr, in smu7_force_dpm_lowest()
2434 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_force_dpm_lowest()
2442 level = phm_get_lowest_enabled_level(hwmgr, in smu7_force_dpm_lowest()
2444 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_force_dpm_lowest()
2452 level = phm_get_lowest_enabled_level(hwmgr, in smu7_force_dpm_lowest()
2454 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_force_dpm_lowest()
2463 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr, in smu7_force_dpm_level() argument
2470 ret = smu7_force_dpm_highest(hwmgr); in smu7_force_dpm_level()
2475 ret = smu7_force_dpm_lowest(hwmgr); in smu7_force_dpm_level()
2480 ret = smu7_unforce_dpm_levels(hwmgr); in smu7_force_dpm_level()
2488 hwmgr->dpm_level = level; in smu7_force_dpm_level()
2493 static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr) in smu7_get_power_state_size() argument
2499 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, in smu7_apply_state_adjust_rules() argument
2514 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_apply_state_adjust_rules()
2516 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_apply_state_adjust_rules()
2527 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ? in smu7_apply_state_adjust_rules()
2528 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : in smu7_apply_state_adjust_rules()
2529 &(hwmgr->dyn_state.max_clock_voltage_on_dc); in smu7_apply_state_adjust_rules()
2532 if (PP_PowerSource_DC == hwmgr->power_source) { in smu7_apply_state_adjust_rules()
2541 smu7_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk; in smu7_apply_state_adjust_rules()
2542 smu7_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk; in smu7_apply_state_adjust_rules()
2544 cgs_get_active_displays_info(hwmgr->device, &info); in smu7_apply_state_adjust_rules()
2548 minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock; in smu7_apply_state_adjust_rules()
2549 minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; in smu7_apply_state_adjust_rules()
2551 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_apply_state_adjust_rules()
2553 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); in smu7_apply_state_adjust_rules()
2575 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk) in smu7_apply_state_adjust_rules()
2576 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk; in smu7_apply_state_adjust_rules()
2578 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk) in smu7_apply_state_adjust_rules()
2579 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk; in smu7_apply_state_adjust_rules()
2581 smu7_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold; in smu7_apply_state_adjust_rules()
2583 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) { in smu7_apply_state_adjust_rules()
2584 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= in smu7_apply_state_adjust_rules()
2585 hwmgr->platform_descriptor.overdriveLimit.engineClock), in smu7_apply_state_adjust_rules()
2587 hwmgr->gfx_arbiter.sclk_over_drive = in smu7_apply_state_adjust_rules()
2588 hwmgr->platform_descriptor.overdriveLimit.engineClock); in smu7_apply_state_adjust_rules()
2590 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk) in smu7_apply_state_adjust_rules()
2592 hwmgr->gfx_arbiter.sclk_over_drive; in smu7_apply_state_adjust_rules()
2595 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) { in smu7_apply_state_adjust_rules()
2596 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= in smu7_apply_state_adjust_rules()
2597 hwmgr->platform_descriptor.overdriveLimit.memoryClock), in smu7_apply_state_adjust_rules()
2599 hwmgr->gfx_arbiter.mclk_over_drive = in smu7_apply_state_adjust_rules()
2600 hwmgr->platform_descriptor.overdriveLimit.memoryClock); in smu7_apply_state_adjust_rules()
2602 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk) in smu7_apply_state_adjust_rules()
2604 hwmgr->gfx_arbiter.mclk_over_drive; in smu7_apply_state_adjust_rules()
2608 hwmgr->platform_descriptor.platformCaps, in smu7_apply_state_adjust_rules()
2652 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_apply_state_adjust_rules()
2665 static int smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) in smu7_dpm_get_mclk() argument
2670 if (hwmgr == NULL) in smu7_dpm_get_mclk()
2673 ps = hwmgr->request_ps; in smu7_dpm_get_mclk()
2687 static int smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) in smu7_dpm_get_sclk() argument
2692 if (hwmgr == NULL) in smu7_dpm_get_sclk()
2695 ps = hwmgr->request_ps; in smu7_dpm_get_sclk()
2709 static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, in smu7_dpm_patch_boot_state() argument
2712 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_dpm_patch_boot_state()
2723 hwmgr->device, index, in smu7_dpm_patch_boot_state()
2741 smu7_get_current_pcie_speed(hwmgr); in smu7_dpm_patch_boot_state()
2744 (uint16_t)smu7_get_current_pcie_lane_number(hwmgr); in smu7_dpm_patch_boot_state()
2755 static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr) in smu7_get_number_of_powerplay_table_entries() argument
2760 if (hwmgr->pp_table_version == PP_TABLE_V0) { in smu7_get_number_of_powerplay_table_entries()
2761 result = pp_tables_get_num_of_entries(hwmgr, &ret); in smu7_get_number_of_powerplay_table_entries()
2763 } else if (hwmgr->pp_table_version == PP_TABLE_V1) { in smu7_get_number_of_powerplay_table_entries()
2764 result = get_number_of_powerplay_table_entries_v1_0(hwmgr); in smu7_get_number_of_powerplay_table_entries()
2770 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr, in smu7_get_pp_table_entry_callback_func_v1() argument
2774 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_get_pp_table_entry_callback_func_v1()
2824 …(smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS… in smu7_get_pp_table_entry_callback_func_v1()
2830 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), in smu7_get_pp_table_entry_callback_func_v1()
2868 static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr, in smu7_get_pp_table_entry_v1() argument
2873 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_get_pp_table_entry_v1()
2875 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_get_pp_table_entry_v1()
2883 result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state, in smu7_get_pp_table_entry_v1()
2970 static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr, in smu7_get_pp_table_entry_callback_func_v0() argument
2974 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_get_pp_table_entry_callback_func_v0()
2988 (ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)), in smu7_get_pp_table_entry_callback_func_v0()
2994 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), in smu7_get_pp_table_entry_callback_func_v0()
3013 static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr, in smu7_get_pp_table_entry_v0() argument
3018 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_get_pp_table_entry_v0()
3020 hwmgr->dyn_state.vddci_dependency_on_mclk; in smu7_get_pp_table_entry_v0()
3028 result = pp_tables_get_entry(hwmgr, entry_index, state, in smu7_get_pp_table_entry_v0()
3120 static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr, in smu7_get_pp_table_entry() argument
3123 if (hwmgr->pp_table_version == PP_TABLE_V0) in smu7_get_pp_table_entry()
3124 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state); in smu7_get_pp_table_entry()
3125 else if (hwmgr->pp_table_version == PP_TABLE_V1) in smu7_get_pp_table_entry()
3126 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state); in smu7_get_pp_table_entry()
3131 static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value) in smu7_read_sensor() argument
3135 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_read_sensor()
3139 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); in smu7_read_sensor()
3140 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); in smu7_read_sensor()
3144 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); in smu7_read_sensor()
3145 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); in smu7_read_sensor()
3149 offset = data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, in smu7_read_sensor()
3153 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); in smu7_read_sensor()
3159 *value = smu7_thermal_get_temperature(hwmgr); in smu7_read_sensor()
3172 static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) in smu7_find_dpm_states_clocks_in_dpm_table() argument
3178 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_find_dpm_states_clocks_in_dpm_table()
3216 cgs_get_active_displays_info(hwmgr->device, &info); in smu7_find_dpm_states_clocks_in_dpm_table()
3224 static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr, in smu7_get_maximum_link_speed() argument
3229 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_get_maximum_link_speed()
3250 struct pp_hwmgr *hwmgr, const void *input) in smu7_request_link_speed_change_before_state_change() argument
3254 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_request_link_speed_change_before_state_change()
3260 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps); in smu7_request_link_speed_change_before_state_change()
3264 current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps); in smu7_request_link_speed_change_before_state_change()
3274 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false)) in smu7_request_link_speed_change_before_state_change()
3280 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false)) in smu7_request_link_speed_change_before_state_change()
3283 data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr); in smu7_request_link_speed_change_before_state_change()
3294 static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) in smu7_freeze_sclk_mclk_dpm() argument
3296 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_freeze_sclk_mclk_dpm()
3304 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), in smu7_freeze_sclk_mclk_dpm()
3307 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, in smu7_freeze_sclk_mclk_dpm()
3316 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), in smu7_freeze_sclk_mclk_dpm()
3319 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, in smu7_freeze_sclk_mclk_dpm()
3329 struct pp_hwmgr *hwmgr, const void *input) in smu7_populate_and_upload_sclk_mclk_dpm_levels() argument
3336 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_populate_and_upload_sclk_mclk_dpm_levels()
3354 …if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) … in smu7_populate_and_upload_sclk_mclk_dpm_levels()
3355 … phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()
3400 …if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) … in smu7_populate_and_upload_sclk_mclk_dpm_levels()
3401 … phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()
3439 result = smum_populate_all_graphic_levels(hwmgr); in smu7_populate_and_upload_sclk_mclk_dpm_levels()
3448 result = smum_populate_all_memory_levels(hwmgr); in smu7_populate_and_upload_sclk_mclk_dpm_levels()
3457 static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr, in smu7_trim_single_dpm_states() argument
3474 static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr, in smu7_trim_dpm_states() argument
3477 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_trim_dpm_states()
3486 smu7_trim_single_dpm_states(hwmgr, in smu7_trim_dpm_states()
3491 smu7_trim_single_dpm_states(hwmgr, in smu7_trim_dpm_states()
3500 struct pp_hwmgr *hwmgr, const void *input) in smu7_generate_dpm_level_enable_mask() argument
3505 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_generate_dpm_level_enable_mask()
3509 result = smu7_trim_dpm_states(hwmgr, smu7_ps); in smu7_generate_dpm_level_enable_mask()
3523 static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) in smu7_unfreeze_sclk_mclk_dpm() argument
3525 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_unfreeze_sclk_mclk_dpm()
3534 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), in smu7_unfreeze_sclk_mclk_dpm()
3537 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, in smu7_unfreeze_sclk_mclk_dpm()
3546 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), in smu7_unfreeze_sclk_mclk_dpm()
3549 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, in smu7_unfreeze_sclk_mclk_dpm()
3561 struct pp_hwmgr *hwmgr, const void *input) in smu7_notify_link_speed_change_after_state_change() argument
3565 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_notify_link_speed_change_after_state_change()
3568 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps); in smu7_notify_link_speed_change_after_state_change()
3580 smu7_get_current_pcie_speed(hwmgr) > 0) in smu7_notify_link_speed_change_after_state_change()
3583 if (acpi_pcie_perf_request(hwmgr->device, request, false)) { in smu7_notify_link_speed_change_after_state_change()
3594 static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr) in smu7_notify_smc_display() argument
3596 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_notify_smc_display()
3598 if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) in smu7_notify_smc_display()
3599 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_notify_smc_display()
3601 return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL; in smu7_notify_smc_display()
3604 static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) in smu7_set_power_state_tasks() argument
3607 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_set_power_state_tasks()
3609 tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input); in smu7_set_power_state_tasks()
3614 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_set_power_state_tasks()
3617 smu7_request_link_speed_change_before_state_change(hwmgr, input); in smu7_set_power_state_tasks()
3623 tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr); in smu7_set_power_state_tasks()
3627 tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); in smu7_set_power_state_tasks()
3632 tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input); in smu7_set_power_state_tasks()
3637 tmp_result = smum_update_sclk_threshold(hwmgr); in smu7_set_power_state_tasks()
3642 tmp_result = smu7_notify_smc_display(hwmgr); in smu7_set_power_state_tasks()
3647 tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr); in smu7_set_power_state_tasks()
3652 tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr); in smu7_set_power_state_tasks()
3657 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_set_power_state_tasks()
3660 smu7_notify_link_speed_change_after_state_change(hwmgr, input); in smu7_set_power_state_tasks()
3669 static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) in smu7_set_max_fan_pwm_output() argument
3671 hwmgr->thermal_controller. in smu7_set_max_fan_pwm_output()
3674 if (phm_is_hw_access_blocked(hwmgr)) in smu7_set_max_fan_pwm_output()
3677 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_set_max_fan_pwm_output()
3681 int smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) in smu7_notify_smc_display_change() argument
3685 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; in smu7_notify_smc_display_change()
3688 int smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) in smu7_notify_smc_display_config_after_ps_adjustment() argument
3694 cgs_get_active_displays_info(hwmgr->device, &info); in smu7_notify_smc_display_config_after_ps_adjustment()
3698 if (num_active_displays > 1 && hwmgr->display_config.multi_monitor_in_sync != true) in smu7_notify_smc_display_config_after_ps_adjustment()
3699 smu7_notify_smc_display_change(hwmgr, false); in smu7_notify_smc_display_config_after_ps_adjustment()
3710 int smu7_program_display_gap(struct pp_hwmgr *hwmgr) in smu7_program_display_gap() argument
3712 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_program_display_gap()
3714 …uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNT… in smu7_program_display_gap()
3724 cgs_get_active_displays_info(hwmgr->device, &info); in smu7_program_display_gap()
3728 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); in smu7_program_display_gap()
3744 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); in smu7_program_display_gap()
3746 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_display_gap()
3747 data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, in smu7_program_display_gap()
3751 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_display_gap()
3752 data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, in smu7_program_display_gap()
3760 int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr) in smu7_display_configuration_changed_task() argument
3762 return smu7_program_display_gap(hwmgr); in smu7_display_configuration_changed_task()
3772 static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm) in smu7_set_max_fan_rpm_output() argument
3774 hwmgr->thermal_controller. in smu7_set_max_fan_rpm_output()
3777 if (phm_is_hw_access_blocked(hwmgr)) in smu7_set_max_fan_rpm_output()
3780 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_set_max_fan_rpm_output()
3784 int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, in smu7_register_internal_thermal_interrupt() argument
3790 bool smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) in smu7_check_smc_update_required_for_display_configuration() argument
3792 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_check_smc_update_required_for_display_configuration()
3796 cgs_get_active_displays_info(hwmgr->device, &info); in smu7_check_smc_update_required_for_display_configuration()
3801 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { in smu7_check_smc_update_required_for_display_configuration()
3802 if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr && in smu7_check_smc_update_required_for_display_configuration()
3804 hwmgr->display_config.min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)) in smu7_check_smc_update_required_for_display_configuration()
3819 int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const … in smu7_check_states_equal() argument
3852 int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr) in smu7_upload_mc_firmware() argument
3854 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_upload_mc_firmware()
3864 smu7_get_mc_microcode_version(hwmgr); in smu7_upload_mc_firmware()
3865 vbios_version = hwmgr->microcode_version_info.MC & 0xf; in smu7_upload_mc_firmware()
3869 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, in smu7_upload_mc_firmware()
3871 tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); in smu7_upload_mc_firmware()
3884 static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr) in smu7_read_clock_registers() argument
3886 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_read_clock_registers()
3889 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); in smu7_read_clock_registers()
3891 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2); in smu7_read_clock_registers()
3893 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3); in smu7_read_clock_registers()
3895 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4); in smu7_read_clock_registers()
3897 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM); in smu7_read_clock_registers()
3899 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2); in smu7_read_clock_registers()
3901 cgs_read_register(hwmgr->device, mmDLL_CNTL); in smu7_read_clock_registers()
3903 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL); in smu7_read_clock_registers()
3905 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL); in smu7_read_clock_registers()
3907 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL); in smu7_read_clock_registers()
3909 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL); in smu7_read_clock_registers()
3911 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1); in smu7_read_clock_registers()
3913 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2); in smu7_read_clock_registers()
3915 cgs_read_register(hwmgr->device, mmMPLL_SS1); in smu7_read_clock_registers()
3917 cgs_read_register(hwmgr->device, mmMPLL_SS2); in smu7_read_clock_registers()
3928 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr) in smu7_get_memory_type() argument
3930 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_get_memory_type()
3933 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0); in smu7_get_memory_type()
3948 static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr) in smu7_enable_acpi_power_management() argument
3950 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_enable_acpi_power_management()
3962 static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr) in smu7_init_power_gate_state() argument
3964 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_init_power_gate_state()
3973 static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr) in smu7_init_sclk_threshold() argument
3975 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_init_sclk_threshold()
3981 int smu7_setup_asic_task(struct pp_hwmgr *hwmgr) in smu7_setup_asic_task() argument
3985 smu7_upload_mc_firmware(hwmgr); in smu7_setup_asic_task()
3987 tmp_result = smu7_read_clock_registers(hwmgr); in smu7_setup_asic_task()
3991 tmp_result = smu7_get_memory_type(hwmgr); in smu7_setup_asic_task()
3995 tmp_result = smu7_enable_acpi_power_management(hwmgr); in smu7_setup_asic_task()
3999 tmp_result = smu7_init_power_gate_state(hwmgr); in smu7_setup_asic_task()
4003 tmp_result = smu7_get_mc_microcode_version(hwmgr); in smu7_setup_asic_task()
4007 tmp_result = smu7_init_sclk_threshold(hwmgr); in smu7_setup_asic_task()
4014 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, in smu7_force_clock_level() argument
4017 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_force_clock_level()
4019 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) in smu7_force_clock_level()
4025 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_force_clock_level()
4031 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_force_clock_level()
4044 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_force_clock_level()
4056 static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, in smu7_print_clock_levels() argument
4059 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_print_clock_levels()
4068 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); in smu7_print_clock_levels()
4069 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); in smu7_print_clock_levels()
4084 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); in smu7_print_clock_levels()
4085 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); in smu7_print_clock_levels()
4100 pcie_speed = smu7_get_current_pcie_speed(hwmgr); in smu7_print_clock_levels()
4121 static int smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) in smu7_set_fan_control_mode() argument
4125 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_set_fan_control_mode()
4127 smu7_fan_ctrl_stop_smc_fan_control(hwmgr); in smu7_set_fan_control_mode()
4128 smu7_fan_ctrl_set_static_mode(hwmgr, mode); in smu7_set_fan_control_mode()
4131 smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr); in smu7_set_fan_control_mode()
4136 static int smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr) in smu7_get_fan_control_mode() argument
4138 if (hwmgr->fan_ctrl_is_in_default_mode) in smu7_get_fan_control_mode()
4139 return hwmgr->fan_ctrl_default_mode; in smu7_get_fan_control_mode()
4141 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_get_fan_control_mode()
4145 static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr) in smu7_get_sclk_od() argument
4147 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_get_sclk_od()
4161 static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) in smu7_set_sclk_od() argument
4163 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_set_sclk_od()
4172 ps = hwmgr->request_ps; in smu7_set_sclk_od()
4187 static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr) in smu7_get_mclk_od() argument
4189 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_get_mclk_od()
4203 static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) in smu7_set_mclk_od() argument
4205 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_set_mclk_od()
4214 ps = hwmgr->request_ps; in smu7_set_mclk_od()
4230 static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) in smu7_get_sclks() argument
4233 (struct phm_ppt_v1_information *)hwmgr->pptable; in smu7_get_sclks()
4238 if (hwmgr->pp_table_version == PP_TABLE_V1) { in smu7_get_sclks()
4246 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { in smu7_get_sclks()
4247 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_get_sclks()
4257 static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk) in smu7_get_mem_latency() argument
4259 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in smu7_get_mem_latency()
4269 static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) in smu7_get_mclks() argument
4272 (struct phm_ppt_v1_information *)hwmgr->pptable; in smu7_get_mclks()
4277 if (hwmgr->pp_table_version == PP_TABLE_V1) { in smu7_get_mclks()
4283 clocks->latency[i] = smu7_get_mem_latency(hwmgr, in smu7_get_mclks()
4287 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { in smu7_get_mclks()
4288 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; in smu7_get_mclks()
4297 static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, in smu7_get_clock_by_type() argument
4302 smu7_get_sclks(hwmgr, clocks); in smu7_get_clock_by_type()
4305 smu7_get_mclks(hwmgr, clocks); in smu7_get_clock_by_type()
4380 int smu7_hwmgr_init(struct pp_hwmgr *hwmgr) in smu7_hwmgr_init() argument
4384 hwmgr->hwmgr_func = &smu7_hwmgr_funcs; in smu7_hwmgr_init()
4385 if (hwmgr->pp_table_version == PP_TABLE_V0) in smu7_hwmgr_init()
4386 hwmgr->pptable_func = &pptable_funcs; in smu7_hwmgr_init()
4387 else if (hwmgr->pp_table_version == PP_TABLE_V1) in smu7_hwmgr_init()
4388 hwmgr->pptable_func = &pptable_v1_0_funcs; in smu7_hwmgr_init()
4390 pp_smu7_thermal_initialize(hwmgr); in smu7_hwmgr_init()