161 		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable);  in smu7_enable_smc_voltage_controller()
298 	tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDC);  in smu7_construct_voltage_tables()
305 	tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX);  in smu7_construct_voltage_tables()
312 	tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDCI);  in smu7_construct_voltage_tables()
319 	tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_MVDD);  in smu7_construct_voltage_tables()
491 	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);  in smu7_reset_to_default()
549 	tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_LINK);  in smu7_setup_default_pcie_table()
623 				smum_get_mac_definition(hwmgr->smumgr,  in smu7_reset_dpm_tables()
628 			smum_get_mac_definition(hwmgr->smumgr,  in smu7_reset_dpm_tables()
633 				smum_get_mac_definition(hwmgr->smumgr,  in smu7_reset_dpm_tables()
638 			smum_get_mac_definition(hwmgr->smumgr,  in smu7_reset_dpm_tables()
643 				smum_get_mac_definition(hwmgr->smumgr,  in smu7_reset_dpm_tables()
853 		return smum_send_msg_to_smc(hwmgr->smumgr,  in smu7_enable_vrhot_gpio_interrupt()
871 		return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);  in smu7_enable_ulv()
881 		return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);  in smu7_disable_ulv()
890 		if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))  in smu7_enable_deep_sleep_master_switch()
895 		if (smum_send_msg_to_smc(hwmgr->smumgr,  in smu7_enable_deep_sleep_master_switch()
910 		if (smum_send_msg_to_smc(hwmgr->smumgr,  in smu7_disable_deep_sleep_master_switch()
926 				+ smum_get_offsetof(hwmgr->smumgr,  in smu7_disable_handshake_uvd()
931 	soft_register_value |= smum_get_mac_definition(hwmgr->smumgr,  in smu7_disable_handshake_uvd()
945 		(0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),  in smu7_enable_sclk_mclk_dpm()
954 				(0 == smum_send_msg_to_smc(hwmgr->smumgr,  in smu7_enable_sclk_mclk_dpm()
991 			smum_get_offsetof(hwmgr->smumgr, SMU_SoftRegisters,  in smu7_start_dpm()
997 			(0 == smum_send_msg_to_smc(hwmgr->smumgr,  in smu7_start_dpm()
1011 				(0 == smum_send_msg_to_smc(hwmgr->smumgr,  in smu7_start_dpm()
1019 		PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,  in smu7_start_dpm()
1037 		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Disable);  in smu7_disable_sclk_mclk_dpm()
1045 		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_Disable);  in smu7_disable_sclk_mclk_dpm()
1065 				(smum_send_msg_to_smc(hwmgr->smumgr,  in smu7_stop_dpm()
1077 	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Disable);  in smu7_stop_dpm()
1231 	smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_NoDisplay);  in smu7_enable_dpm_tasks()
1312 		PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableAvfs)),  in smu7_disable_dpm_tasks()
1656 	i = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX);  in phm_add_voltage()
2348 				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_force_dpm_highest()
2361 				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_force_dpm_highest()
2375 				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_force_dpm_highest()
2394 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_upload_dpm_level_enable_mask()
2401 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_upload_dpm_level_enable_mask()
2417 		smum_send_msg_to_smc(hwmgr->smumgr,  in smu7_unforce_dpm_levels()
2434 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_force_dpm_lowest()
2444 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_force_dpm_lowest()
2454 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_force_dpm_lowest()
2824 …(smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS…  in smu7_get_pp_table_entry_callback_func_v1()
2988 			(ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),  in smu7_get_pp_table_entry_callback_func_v0()
3139 		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);  in smu7_read_sensor()
3144 		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);  in smu7_read_sensor()
3149 		offset = data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,  in smu7_read_sensor()
3307 		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,  in smu7_freeze_sclk_mclk_dpm()
3319 		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,  in smu7_freeze_sclk_mclk_dpm()
3537 		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,  in smu7_unfreeze_sclk_mclk_dpm()
3549 		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,  in smu7_unfreeze_sclk_mclk_dpm()
3599 		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_notify_smc_display()
3601 	return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ?  0 : -EINVAL;  in smu7_notify_smc_display()
3677 	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_set_max_fan_pwm_output()
3685 	return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;  in smu7_notify_smc_display_change()
3747 			data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,  in smu7_program_display_gap()
3752 			data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,  in smu7_program_display_gap()
3780 	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_set_max_fan_rpm_output()
4025 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_force_clock_level()
4031 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_force_clock_level()
4044 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,  in smu7_force_clock_level()
4068 		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);  in smu7_print_clock_levels()
4084 		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);  in smu7_print_clock_levels()