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Lines Matching refs:reg

31 	u32 reg;  in analogix_dp_enable_video_mute()  local
34 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
35 reg |= HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
36 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
38 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
39 reg &= ~HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
40 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
46 u32 reg; in analogix_dp_stop_video() local
48 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
49 reg &= ~VIDEO_EN; in analogix_dp_stop_video()
50 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
55 u32 reg; in analogix_dp_lane_swap() local
58 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | in analogix_dp_lane_swap()
61 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | in analogix_dp_lane_swap()
64 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); in analogix_dp_lane_swap()
69 u32 reg; in analogix_dp_init_analog_param() local
71 reg = TX_TERMINAL_CTRL_50_OHM; in analogix_dp_init_analog_param()
72 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); in analogix_dp_init_analog_param()
74 reg = SEL_24M | TX_DVDD_BIT_1_0625V; in analogix_dp_init_analog_param()
75 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); in analogix_dp_init_analog_param()
78 reg = REF_CLK_24M; in analogix_dp_init_analog_param()
80 reg ^= REF_CLK_MASK; in analogix_dp_init_analog_param()
82 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); in analogix_dp_init_analog_param()
89 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; in analogix_dp_init_analog_param()
90 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3); in analogix_dp_init_analog_param()
92 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | in analogix_dp_init_analog_param()
94 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1); in analogix_dp_init_analog_param()
96 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | in analogix_dp_init_analog_param()
98 writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL); in analogix_dp_init_analog_param()
123 u32 reg; in analogix_dp_reset() local
128 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | in analogix_dp_reset()
131 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); in analogix_dp_reset()
133 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | in analogix_dp_reset()
136 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_reset()
173 u32 reg; in analogix_dp_config_interrupt() local
176 reg = COMMON_INT_MASK_1; in analogix_dp_config_interrupt()
177 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); in analogix_dp_config_interrupt()
179 reg = COMMON_INT_MASK_2; in analogix_dp_config_interrupt()
180 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); in analogix_dp_config_interrupt()
182 reg = COMMON_INT_MASK_3; in analogix_dp_config_interrupt()
183 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); in analogix_dp_config_interrupt()
185 reg = COMMON_INT_MASK_4; in analogix_dp_config_interrupt()
186 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); in analogix_dp_config_interrupt()
188 reg = INT_STA_MASK; in analogix_dp_config_interrupt()
189 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); in analogix_dp_config_interrupt()
194 u32 reg; in analogix_dp_mute_hpd_interrupt() local
197 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); in analogix_dp_mute_hpd_interrupt()
198 reg &= ~COMMON_INT_MASK_4; in analogix_dp_mute_hpd_interrupt()
199 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); in analogix_dp_mute_hpd_interrupt()
201 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK); in analogix_dp_mute_hpd_interrupt()
202 reg &= ~INT_STA_MASK; in analogix_dp_mute_hpd_interrupt()
203 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); in analogix_dp_mute_hpd_interrupt()
208 u32 reg; in analogix_dp_unmute_hpd_interrupt() local
211 reg = COMMON_INT_MASK_4; in analogix_dp_unmute_hpd_interrupt()
212 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); in analogix_dp_unmute_hpd_interrupt()
214 reg = INT_STA_MASK; in analogix_dp_unmute_hpd_interrupt()
215 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); in analogix_dp_unmute_hpd_interrupt()
220 u32 reg; in analogix_dp_get_pll_lock_status() local
222 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); in analogix_dp_get_pll_lock_status()
223 if (reg & PLL_LOCK) in analogix_dp_get_pll_lock_status()
231 u32 reg; in analogix_dp_set_pll_power_down() local
234 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); in analogix_dp_set_pll_power_down()
235 reg |= DP_PLL_PD; in analogix_dp_set_pll_power_down()
236 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); in analogix_dp_set_pll_power_down()
238 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); in analogix_dp_set_pll_power_down()
239 reg &= ~DP_PLL_PD; in analogix_dp_set_pll_power_down()
240 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); in analogix_dp_set_pll_power_down()
248 u32 reg; in analogix_dp_set_analog_power_down() local
257 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
258 reg |= AUX_PD; in analogix_dp_set_analog_power_down()
259 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
261 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
262 reg &= ~AUX_PD; in analogix_dp_set_analog_power_down()
263 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
268 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
269 reg |= CH0_PD; in analogix_dp_set_analog_power_down()
270 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
272 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
273 reg &= ~CH0_PD; in analogix_dp_set_analog_power_down()
274 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
279 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
280 reg |= CH1_PD; in analogix_dp_set_analog_power_down()
281 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
283 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
284 reg &= ~CH1_PD; in analogix_dp_set_analog_power_down()
285 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
290 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
291 reg |= CH2_PD; in analogix_dp_set_analog_power_down()
292 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
294 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
295 reg &= ~CH2_PD; in analogix_dp_set_analog_power_down()
296 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
301 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
302 reg |= CH3_PD; in analogix_dp_set_analog_power_down()
303 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
305 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
306 reg &= ~CH3_PD; in analogix_dp_set_analog_power_down()
307 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
312 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
313 reg |= DP_PHY_PD; in analogix_dp_set_analog_power_down()
314 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
316 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
317 reg &= ~DP_PHY_PD; in analogix_dp_set_analog_power_down()
318 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
323 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | in analogix_dp_set_analog_power_down()
325 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
337 u32 reg; in analogix_dp_init_analog_func() local
342 reg = PLL_LOCK_CHG; in analogix_dp_init_analog_func()
343 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); in analogix_dp_init_analog_func()
345 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); in analogix_dp_init_analog_func()
346 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); in analogix_dp_init_analog_func()
347 writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL); in analogix_dp_init_analog_func()
364 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_init_analog_func()
365 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N in analogix_dp_init_analog_func()
367 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_init_analog_func()
372 u32 reg; in analogix_dp_clear_hotplug_interrupts() local
377 reg = HOTPLUG_CHG | HPD_LOST | PLUG; in analogix_dp_clear_hotplug_interrupts()
378 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); in analogix_dp_clear_hotplug_interrupts()
380 reg = INT_HPD; in analogix_dp_clear_hotplug_interrupts()
381 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_clear_hotplug_interrupts()
386 u32 reg; in analogix_dp_init_hpd() local
393 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_init_hpd()
394 reg &= ~(F_HPD | HPD_CTRL); in analogix_dp_init_hpd()
395 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_init_hpd()
400 u32 reg; in analogix_dp_force_hpd() local
402 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_force_hpd()
403 reg = (F_HPD | HPD_CTRL); in analogix_dp_force_hpd()
404 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_force_hpd()
409 u32 reg; in analogix_dp_get_irq_type() local
412 reg = gpio_get_value(dp->hpd_gpio); in analogix_dp_get_irq_type()
413 if (reg) in analogix_dp_get_irq_type()
419 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); in analogix_dp_get_irq_type()
421 if (reg & PLUG) in analogix_dp_get_irq_type()
424 if (reg & HPD_LOST) in analogix_dp_get_irq_type()
427 if (reg & HOTPLUG_CHG) in analogix_dp_get_irq_type()
436 u32 reg; in analogix_dp_reset_aux() local
439 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_reset_aux()
440 reg |= AUX_FUNC_EN_N; in analogix_dp_reset_aux()
441 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_reset_aux()
446 u32 reg; in analogix_dp_init_aux() local
449 reg = RPLY_RECEIV | AUX_ERR; in analogix_dp_init_aux()
450 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_init_aux()
456 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | in analogix_dp_init_aux()
460 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | in analogix_dp_init_aux()
463 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL); in analogix_dp_init_aux()
466 reg = DEFER_CTRL_EN | DEFER_COUNT(1); in analogix_dp_init_aux()
467 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL); in analogix_dp_init_aux()
470 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_init_aux()
471 reg &= ~AUX_FUNC_EN_N; in analogix_dp_init_aux()
472 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_init_aux()
477 u32 reg; in analogix_dp_get_plug_in_status() local
483 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_get_plug_in_status()
484 if (reg & HPD_STATUS) in analogix_dp_get_plug_in_status()
493 u32 reg; in analogix_dp_enable_sw_function() local
495 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); in analogix_dp_enable_sw_function()
496 reg &= ~SW_FUNC_EN_N; in analogix_dp_enable_sw_function()
497 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); in analogix_dp_enable_sw_function()
502 int reg; in analogix_dp_start_aux_transaction() local
507 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); in analogix_dp_start_aux_transaction()
508 reg |= AUX_EN; in analogix_dp_start_aux_transaction()
509 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); in analogix_dp_start_aux_transaction()
512 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_start_aux_transaction()
513 while (!(reg & RPLY_RECEIV)) { in analogix_dp_start_aux_transaction()
519 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_start_aux_transaction()
527 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_start_aux_transaction()
528 if (reg & AUX_ERR) { in analogix_dp_start_aux_transaction()
534 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA); in analogix_dp_start_aux_transaction()
535 if ((reg & AUX_STATUS_MASK) != 0) { in analogix_dp_start_aux_transaction()
537 reg & AUX_STATUS_MASK); in analogix_dp_start_aux_transaction()
548 u32 reg; in analogix_dp_write_byte_to_dpcd() local
554 reg = BUF_CLR; in analogix_dp_write_byte_to_dpcd()
555 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); in analogix_dp_write_byte_to_dpcd()
558 reg = AUX_ADDR_7_0(reg_addr); in analogix_dp_write_byte_to_dpcd()
559 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); in analogix_dp_write_byte_to_dpcd()
560 reg = AUX_ADDR_15_8(reg_addr); in analogix_dp_write_byte_to_dpcd()
561 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); in analogix_dp_write_byte_to_dpcd()
562 reg = AUX_ADDR_19_16(reg_addr); in analogix_dp_write_byte_to_dpcd()
563 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); in analogix_dp_write_byte_to_dpcd()
566 reg = (unsigned int)data; in analogix_dp_write_byte_to_dpcd()
567 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0); in analogix_dp_write_byte_to_dpcd()
574 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; in analogix_dp_write_byte_to_dpcd()
575 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); in analogix_dp_write_byte_to_dpcd()
590 u32 reg; in analogix_dp_set_link_bandwidth() local
592 reg = bwtype; in analogix_dp_set_link_bandwidth()
594 writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET); in analogix_dp_set_link_bandwidth()
599 u32 reg; in analogix_dp_get_link_bandwidth() local
601 reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET); in analogix_dp_get_link_bandwidth()
602 *bwtype = reg; in analogix_dp_get_link_bandwidth()
607 u32 reg; in analogix_dp_set_lane_count() local
609 reg = count; in analogix_dp_set_lane_count()
610 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); in analogix_dp_set_lane_count()
615 u32 reg; in analogix_dp_get_lane_count() local
617 reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); in analogix_dp_get_lane_count()
618 *count = reg; in analogix_dp_get_lane_count()
624 u32 reg; in analogix_dp_enable_enhanced_mode() local
627 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_enable_enhanced_mode()
628 reg |= ENHANCED; in analogix_dp_enable_enhanced_mode()
629 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_enable_enhanced_mode()
631 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_enable_enhanced_mode()
632 reg &= ~ENHANCED; in analogix_dp_enable_enhanced_mode()
633 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_enable_enhanced_mode()
640 u32 reg; in analogix_dp_set_training_pattern() local
644 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; in analogix_dp_set_training_pattern()
645 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_set_training_pattern()
648 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; in analogix_dp_set_training_pattern()
649 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_set_training_pattern()
652 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; in analogix_dp_set_training_pattern()
653 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_set_training_pattern()
656 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; in analogix_dp_set_training_pattern()
657 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_set_training_pattern()
660 reg = SCRAMBLING_ENABLE | in analogix_dp_set_training_pattern()
663 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_set_training_pattern()
673 u32 reg; in analogix_dp_set_lane0_pre_emphasis() local
675 reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); in analogix_dp_set_lane0_pre_emphasis()
676 reg &= ~PRE_EMPHASIS_SET_MASK; in analogix_dp_set_lane0_pre_emphasis()
677 reg |= level << PRE_EMPHASIS_SET_SHIFT; in analogix_dp_set_lane0_pre_emphasis()
678 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); in analogix_dp_set_lane0_pre_emphasis()
684 u32 reg; in analogix_dp_set_lane1_pre_emphasis() local
686 reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); in analogix_dp_set_lane1_pre_emphasis()
687 reg &= ~PRE_EMPHASIS_SET_MASK; in analogix_dp_set_lane1_pre_emphasis()
688 reg |= level << PRE_EMPHASIS_SET_SHIFT; in analogix_dp_set_lane1_pre_emphasis()
689 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); in analogix_dp_set_lane1_pre_emphasis()
695 u32 reg; in analogix_dp_set_lane2_pre_emphasis() local
697 reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); in analogix_dp_set_lane2_pre_emphasis()
698 reg &= ~PRE_EMPHASIS_SET_MASK; in analogix_dp_set_lane2_pre_emphasis()
699 reg |= level << PRE_EMPHASIS_SET_SHIFT; in analogix_dp_set_lane2_pre_emphasis()
700 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); in analogix_dp_set_lane2_pre_emphasis()
706 u32 reg; in analogix_dp_set_lane3_pre_emphasis() local
708 reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); in analogix_dp_set_lane3_pre_emphasis()
709 reg &= ~PRE_EMPHASIS_SET_MASK; in analogix_dp_set_lane3_pre_emphasis()
710 reg |= level << PRE_EMPHASIS_SET_SHIFT; in analogix_dp_set_lane3_pre_emphasis()
711 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); in analogix_dp_set_lane3_pre_emphasis()
717 u32 reg; in analogix_dp_set_lane0_link_training() local
719 reg = training_lane; in analogix_dp_set_lane0_link_training()
720 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); in analogix_dp_set_lane0_link_training()
726 u32 reg; in analogix_dp_set_lane1_link_training() local
728 reg = training_lane; in analogix_dp_set_lane1_link_training()
729 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); in analogix_dp_set_lane1_link_training()
735 u32 reg; in analogix_dp_set_lane2_link_training() local
737 reg = training_lane; in analogix_dp_set_lane2_link_training()
738 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); in analogix_dp_set_lane2_link_training()
744 u32 reg; in analogix_dp_set_lane3_link_training() local
746 reg = training_lane; in analogix_dp_set_lane3_link_training()
747 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); in analogix_dp_set_lane3_link_training()
772 u32 reg; in analogix_dp_reset_macro() local
774 reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST); in analogix_dp_reset_macro()
775 reg |= MACRO_RST; in analogix_dp_reset_macro()
776 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); in analogix_dp_reset_macro()
781 reg &= ~MACRO_RST; in analogix_dp_reset_macro()
782 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); in analogix_dp_reset_macro()
787 u32 reg; in analogix_dp_init_video() local
789 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; in analogix_dp_init_video()
790 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); in analogix_dp_init_video()
792 reg = 0x0; in analogix_dp_init_video()
793 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); in analogix_dp_init_video()
795 reg = CHA_CRI(4) | CHA_CTRL; in analogix_dp_init_video()
796 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); in analogix_dp_init_video()
798 reg = 0x0; in analogix_dp_init_video()
799 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_init_video()
801 reg = VID_HRES_TH(2) | VID_VRES_TH(0); in analogix_dp_init_video()
802 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8); in analogix_dp_init_video()
807 u32 reg; in analogix_dp_set_video_color_format() local
810 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | in analogix_dp_set_video_color_format()
813 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2); in analogix_dp_set_video_color_format()
816 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); in analogix_dp_set_video_color_format()
817 reg &= ~IN_YC_COEFFI_MASK; in analogix_dp_set_video_color_format()
819 reg |= IN_YC_COEFFI_ITU709; in analogix_dp_set_video_color_format()
821 reg |= IN_YC_COEFFI_ITU601; in analogix_dp_set_video_color_format()
822 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); in analogix_dp_set_video_color_format()
827 u32 reg; in analogix_dp_is_slave_video_stream_clock_on() local
829 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); in analogix_dp_is_slave_video_stream_clock_on()
830 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); in analogix_dp_is_slave_video_stream_clock_on()
832 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); in analogix_dp_is_slave_video_stream_clock_on()
834 if (!(reg & DET_STA)) { in analogix_dp_is_slave_video_stream_clock_on()
839 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); in analogix_dp_is_slave_video_stream_clock_on()
840 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); in analogix_dp_is_slave_video_stream_clock_on()
842 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); in analogix_dp_is_slave_video_stream_clock_on()
845 if (reg & CHA_STA) { in analogix_dp_is_slave_video_stream_clock_on()
857 u32 reg; in analogix_dp_set_video_cr_mn() local
860 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_set_video_cr_mn()
861 reg |= FIX_M_VID; in analogix_dp_set_video_cr_mn()
862 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_set_video_cr_mn()
863 reg = m_value & 0xff; in analogix_dp_set_video_cr_mn()
864 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0); in analogix_dp_set_video_cr_mn()
865 reg = (m_value >> 8) & 0xff; in analogix_dp_set_video_cr_mn()
866 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1); in analogix_dp_set_video_cr_mn()
867 reg = (m_value >> 16) & 0xff; in analogix_dp_set_video_cr_mn()
868 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2); in analogix_dp_set_video_cr_mn()
870 reg = n_value & 0xff; in analogix_dp_set_video_cr_mn()
871 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0); in analogix_dp_set_video_cr_mn()
872 reg = (n_value >> 8) & 0xff; in analogix_dp_set_video_cr_mn()
873 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1); in analogix_dp_set_video_cr_mn()
874 reg = (n_value >> 16) & 0xff; in analogix_dp_set_video_cr_mn()
875 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2); in analogix_dp_set_video_cr_mn()
877 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_set_video_cr_mn()
878 reg &= ~FIX_M_VID; in analogix_dp_set_video_cr_mn()
879 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); in analogix_dp_set_video_cr_mn()
889 u32 reg; in analogix_dp_set_video_timing_mode() local
892 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_set_video_timing_mode()
893 reg &= ~FORMAT_SEL; in analogix_dp_set_video_timing_mode()
894 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_set_video_timing_mode()
896 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_set_video_timing_mode()
897 reg |= FORMAT_SEL; in analogix_dp_set_video_timing_mode()
898 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_set_video_timing_mode()
904 u32 reg; in analogix_dp_enable_video_master() local
907 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); in analogix_dp_enable_video_master()
908 reg &= ~VIDEO_MODE_MASK; in analogix_dp_enable_video_master()
909 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; in analogix_dp_enable_video_master()
910 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); in analogix_dp_enable_video_master()
912 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); in analogix_dp_enable_video_master()
913 reg &= ~VIDEO_MODE_MASK; in analogix_dp_enable_video_master()
914 reg |= VIDEO_MODE_SLAVE_MODE; in analogix_dp_enable_video_master()
915 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); in analogix_dp_enable_video_master()
921 u32 reg; in analogix_dp_start_video() local
923 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_start_video()
924 reg |= VIDEO_EN; in analogix_dp_start_video()
925 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_start_video()
930 u32 reg; in analogix_dp_is_video_stream_on() local
932 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_is_video_stream_on()
933 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_is_video_stream_on()
935 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); in analogix_dp_is_video_stream_on()
936 if (!(reg & STRM_VALID)) { in analogix_dp_is_video_stream_on()
946 u32 reg; in analogix_dp_config_video_slave_mode() local
948 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); in analogix_dp_config_video_slave_mode()
949 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); in analogix_dp_config_video_slave_mode()
950 reg |= MASTER_VID_FUNC_EN_N; in analogix_dp_config_video_slave_mode()
951 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); in analogix_dp_config_video_slave_mode()
953 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_config_video_slave_mode()
954 reg &= ~INTERACE_SCAN_CFG; in analogix_dp_config_video_slave_mode()
955 reg |= (dp->video_info.interlaced << 2); in analogix_dp_config_video_slave_mode()
956 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_config_video_slave_mode()
958 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_config_video_slave_mode()
959 reg &= ~VSYNC_POLARITY_CFG; in analogix_dp_config_video_slave_mode()
960 reg |= (dp->video_info.v_sync_polarity << 1); in analogix_dp_config_video_slave_mode()
961 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_config_video_slave_mode()
963 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_config_video_slave_mode()
964 reg &= ~HSYNC_POLARITY_CFG; in analogix_dp_config_video_slave_mode()
965 reg |= (dp->video_info.h_sync_polarity << 0); in analogix_dp_config_video_slave_mode()
966 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); in analogix_dp_config_video_slave_mode()
968 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; in analogix_dp_config_video_slave_mode()
969 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); in analogix_dp_config_video_slave_mode()
974 u32 reg; in analogix_dp_enable_scrambling() local
976 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_enable_scrambling()
977 reg &= ~SCRAMBLING_DISABLE; in analogix_dp_enable_scrambling()
978 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_enable_scrambling()
983 u32 reg; in analogix_dp_disable_scrambling() local
985 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_disable_scrambling()
986 reg |= SCRAMBLING_DISABLE; in analogix_dp_disable_scrambling()
987 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); in analogix_dp_disable_scrambling()
1044 u32 reg; in analogix_dp_transfer() local
1055 reg = BUF_CLR; in analogix_dp_transfer()
1056 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); in analogix_dp_transfer()
1060 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_I2C_TRANSACTION; in analogix_dp_transfer()
1062 reg |= AUX_TX_COMM_MOT; in analogix_dp_transfer()
1066 reg = AUX_TX_COMM_READ | AUX_TX_COMM_I2C_TRANSACTION; in analogix_dp_transfer()
1068 reg |= AUX_TX_COMM_MOT; in analogix_dp_transfer()
1072 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_DP_TRANSACTION; in analogix_dp_transfer()
1076 reg = AUX_TX_COMM_READ | AUX_TX_COMM_DP_TRANSACTION; in analogix_dp_transfer()
1083 reg |= AUX_LENGTH(msg->size); in analogix_dp_transfer()
1084 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); in analogix_dp_transfer()
1087 reg = AUX_ADDR_7_0(msg->address); in analogix_dp_transfer()
1088 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); in analogix_dp_transfer()
1089 reg = AUX_ADDR_15_8(msg->address); in analogix_dp_transfer()
1090 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); in analogix_dp_transfer()
1091 reg = AUX_ADDR_19_16(msg->address); in analogix_dp_transfer()
1092 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); in analogix_dp_transfer()
1096 reg = buffer[i]; in analogix_dp_transfer()
1097 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + in analogix_dp_transfer()
1104 reg = AUX_EN; in analogix_dp_transfer()
1108 reg |= ADDR_ONLY; in analogix_dp_transfer()
1110 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); in analogix_dp_transfer()
1114 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_transfer()
1115 while (!(reg & RPLY_RECEIV)) { in analogix_dp_transfer()
1121 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_transfer()
1129 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); in analogix_dp_transfer()
1130 if (reg & AUX_ERR) { in analogix_dp_transfer()
1136 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA); in analogix_dp_transfer()
1137 if ((reg & AUX_STATUS_MASK)) { in analogix_dp_transfer()
1139 reg & AUX_STATUS_MASK); in analogix_dp_transfer()
1145 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + in analogix_dp_transfer()
1147 buffer[i] = (unsigned char)reg; in analogix_dp_transfer()
1153 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM); in analogix_dp_transfer()
1154 if (reg == AUX_RX_COMM_AUX_DEFER) in analogix_dp_transfer()
1156 else if (reg == AUX_RX_COMM_I2C_DEFER) in analogix_dp_transfer()