86 	REG_WRITE(map->stride, crtc->primary->fb->pitches[0]);  in gma_pipe_set_base()
110 	REG_WRITE(map->cntr, dspcntr);  in gma_pipe_set_base()
119 		REG_WRITE(map->base, offset + start);  in gma_pipe_set_base()
122 		REG_WRITE(map->base, offset);  in gma_pipe_set_base()
124 		REG_WRITE(map->surf, start);  in gma_pipe_set_base()
154 			REG_WRITE(palreg + 4 * i,  in gma_crtc_load_lut()
229 			REG_WRITE(map->dpll, temp);  in gma_crtc_dpms()
233 			REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);  in gma_crtc_dpms()
237 			REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);  in gma_crtc_dpms()
246 			REG_WRITE(map->cntr,  in gma_crtc_dpms()
249 			REG_WRITE(map->base, REG_READ(map->base));  in gma_crtc_dpms()
257 			REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);  in gma_crtc_dpms()
262 		REG_WRITE(map->status, temp);  in gma_crtc_dpms()
282 		REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);  in gma_crtc_dpms()
293 			REG_WRITE(map->cntr,  in gma_crtc_dpms()
296 			REG_WRITE(map->base, REG_READ(map->base));  in gma_crtc_dpms()
303 			REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);  in gma_crtc_dpms()
315 			REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);  in gma_crtc_dpms()
328 	REG_WRITE(DSPARB, 0x3F3E);  in gma_crtc_dpms()
354 			REG_WRITE(control, temp);  in gma_crtc_cursor_set()
355 			REG_WRITE(base, 0);  in gma_crtc_cursor_set()
431 		REG_WRITE(control, temp);  in gma_crtc_cursor_set()
432 		REG_WRITE(base, addr);  in gma_crtc_cursor_set()
475 		REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);  in gma_crtc_cursor_move()
476 		REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);  in gma_crtc_cursor_move()
594 		REG_WRITE(map->dpll,  in gma_crtc_restore()
600 	REG_WRITE(map->fp0, crtc_state->saveFP0);  in gma_crtc_restore()
603 	REG_WRITE(map->fp1, crtc_state->saveFP1);  in gma_crtc_restore()
606 	REG_WRITE(map->dpll, crtc_state->saveDPLL);  in gma_crtc_restore()
610 	REG_WRITE(map->htotal, crtc_state->saveHTOTAL);  in gma_crtc_restore()
611 	REG_WRITE(map->hblank, crtc_state->saveHBLANK);  in gma_crtc_restore()
612 	REG_WRITE(map->hsync, crtc_state->saveHSYNC);  in gma_crtc_restore()
613 	REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);  in gma_crtc_restore()
614 	REG_WRITE(map->vblank, crtc_state->saveVBLANK);  in gma_crtc_restore()
615 	REG_WRITE(map->vsync, crtc_state->saveVSYNC);  in gma_crtc_restore()
616 	REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);  in gma_crtc_restore()
618 	REG_WRITE(map->size, crtc_state->saveDSPSIZE);  in gma_crtc_restore()
619 	REG_WRITE(map->pos, crtc_state->saveDSPPOS);  in gma_crtc_restore()
621 	REG_WRITE(map->src, crtc_state->savePIPESRC);  in gma_crtc_restore()
622 	REG_WRITE(map->base, crtc_state->saveDSPBASE);  in gma_crtc_restore()
623 	REG_WRITE(map->conf, crtc_state->savePIPECONF);  in gma_crtc_restore()
627 	REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);  in gma_crtc_restore()
628 	REG_WRITE(map->base, crtc_state->saveDSPBASE);  in gma_crtc_restore()
634 		REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]);  in gma_crtc_restore()