Lines Matching refs:batch
820 #define wa_ctx_emit(batch, index, cmd) \ argument
826 batch[__index] = (cmd); \
829 #define wa_ctx_emit_reg(batch, index, reg) \ argument
830 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
849 uint32_t *batch, in gen8_emit_flush_coherentl3_wa() argument
864 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | in gen8_emit_flush_coherentl3_wa()
866 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
867 wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256); in gen8_emit_flush_coherentl3_wa()
868 wa_ctx_emit(batch, index, 0); in gen8_emit_flush_coherentl3_wa()
870 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); in gen8_emit_flush_coherentl3_wa()
871 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
872 wa_ctx_emit(batch, index, l3sqc4_flush); in gen8_emit_flush_coherentl3_wa()
874 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); in gen8_emit_flush_coherentl3_wa()
875 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | in gen8_emit_flush_coherentl3_wa()
877 wa_ctx_emit(batch, index, 0); in gen8_emit_flush_coherentl3_wa()
878 wa_ctx_emit(batch, index, 0); in gen8_emit_flush_coherentl3_wa()
879 wa_ctx_emit(batch, index, 0); in gen8_emit_flush_coherentl3_wa()
880 wa_ctx_emit(batch, index, 0); in gen8_emit_flush_coherentl3_wa()
882 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | in gen8_emit_flush_coherentl3_wa()
884 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
885 wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256); in gen8_emit_flush_coherentl3_wa()
886 wa_ctx_emit(batch, index, 0); in gen8_emit_flush_coherentl3_wa()
927 uint32_t *batch, in gen8_init_indirectctx_bb() argument
934 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); in gen8_init_indirectctx_bb()
938 int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index); in gen8_init_indirectctx_bb()
948 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); in gen8_init_indirectctx_bb()
949 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | in gen8_init_indirectctx_bb()
953 wa_ctx_emit(batch, index, scratch_addr); in gen8_init_indirectctx_bb()
954 wa_ctx_emit(batch, index, 0); in gen8_init_indirectctx_bb()
955 wa_ctx_emit(batch, index, 0); in gen8_init_indirectctx_bb()
956 wa_ctx_emit(batch, index, 0); in gen8_init_indirectctx_bb()
960 wa_ctx_emit(batch, index, MI_NOOP); in gen8_init_indirectctx_bb()
982 uint32_t *batch, in gen8_init_perctx_bb() argument
988 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); in gen8_init_perctx_bb()
990 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); in gen8_init_perctx_bb()
997 uint32_t *batch, in gen9_init_indirectctx_bb() argument
1007 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); in gen9_init_indirectctx_bb()
1010 ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); in gen9_init_indirectctx_bb()
1016 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); in gen9_init_indirectctx_bb()
1017 wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); in gen9_init_indirectctx_bb()
1018 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( in gen9_init_indirectctx_bb()
1020 wa_ctx_emit(batch, index, MI_NOOP); in gen9_init_indirectctx_bb()
1028 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); in gen9_init_indirectctx_bb()
1029 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | in gen9_init_indirectctx_bb()
1033 wa_ctx_emit(batch, index, scratch_addr); in gen9_init_indirectctx_bb()
1034 wa_ctx_emit(batch, index, 0); in gen9_init_indirectctx_bb()
1035 wa_ctx_emit(batch, index, 0); in gen9_init_indirectctx_bb()
1036 wa_ctx_emit(batch, index, 0); in gen9_init_indirectctx_bb()
1055 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE); in gen9_init_indirectctx_bb()
1056 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE); in gen9_init_indirectctx_bb()
1057 wa_ctx_emit(batch, index, eu_pool_config); in gen9_init_indirectctx_bb()
1058 wa_ctx_emit(batch, index, 0); in gen9_init_indirectctx_bb()
1059 wa_ctx_emit(batch, index, 0); in gen9_init_indirectctx_bb()
1060 wa_ctx_emit(batch, index, 0); in gen9_init_indirectctx_bb()
1065 wa_ctx_emit(batch, index, MI_NOOP); in gen9_init_indirectctx_bb()
1072 uint32_t *batch, in gen9_init_perctx_bb() argument
1080 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); in gen9_init_perctx_bb()
1081 wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); in gen9_init_perctx_bb()
1082 wa_ctx_emit(batch, index, in gen9_init_perctx_bb()
1084 wa_ctx_emit(batch, index, MI_NOOP); in gen9_init_perctx_bb()
1089 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4)); in gen9_init_perctx_bb()
1091 wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK); in gen9_init_perctx_bb()
1092 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); in gen9_init_perctx_bb()
1094 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1); in gen9_init_perctx_bb()
1095 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); in gen9_init_perctx_bb()
1097 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2); in gen9_init_perctx_bb()
1098 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); in gen9_init_perctx_bb()
1100 wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2); in gen9_init_perctx_bb()
1102 wa_ctx_emit(batch, index, 0x0); in gen9_init_perctx_bb()
1103 wa_ctx_emit(batch, index, MI_NOOP); in gen9_init_perctx_bb()
1109 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); in gen9_init_perctx_bb()
1111 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); in gen9_init_perctx_bb()
1152 uint32_t *batch; in intel_init_workaround_bb() local
1179 batch = kmap_atomic(page); in intel_init_workaround_bb()
1185 batch, in intel_init_workaround_bb()
1192 batch, in intel_init_workaround_bb()
1199 batch, in intel_init_workaround_bb()
1206 batch, in intel_init_workaround_bb()
1213 kunmap_atomic(batch); in intel_init_workaround_bb()