Lines Matching refs:level
960 int level) in vlv_compute_wm_level() argument
965 if (dev_priv->wm.pri_latency[level] == 0) in vlv_compute_wm_level()
988 dev_priv->wm.pri_latency[level] * 10); in vlv_compute_wm_level()
1064 int level; in vlv_invert_wms() local
1066 for (level = 0; level < wm_state->num_levels; level++) { in vlv_invert_wms()
1071 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; in vlv_invert_wms()
1072 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor; in vlv_invert_wms()
1078 wm_state->wm[level].cursor = plane->wm.fifo_size - in vlv_invert_wms()
1079 wm_state->wm[level].cursor; in vlv_invert_wms()
1082 wm_state->wm[level].primary = plane->wm.fifo_size - in vlv_invert_wms()
1083 wm_state->wm[level].primary; in vlv_invert_wms()
1087 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - in vlv_invert_wms()
1088 wm_state->wm[level].sprite[sprite]; in vlv_invert_wms()
1101 int level; in vlv_compute_wm() local
1116 for (level = 0; level < wm_state->num_levels; level++) { in vlv_compute_wm()
1117 wm_state->sr[level].plane = sr_fifo_size; in vlv_compute_wm()
1118 wm_state->sr[level].cursor = 63; in vlv_compute_wm()
1130 for (level = 0; level < wm_state->num_levels; level++) { in vlv_compute_wm()
1131 int wm = vlv_compute_wm_level(plane, crtc, state, level); in vlv_compute_wm()
1135 if (WARN_ON(level == 0 && wm > max_wm)) in vlv_compute_wm()
1144 wm_state->wm[level].cursor = wm; in vlv_compute_wm()
1147 wm_state->wm[level].primary = wm; in vlv_compute_wm()
1151 wm_state->wm[level].sprite[sprite] = wm; in vlv_compute_wm()
1156 wm_state->num_levels = level; in vlv_compute_wm()
1163 int sprite, level; in vlv_compute_wm() local
1165 for (level = 0; level < wm_state->num_levels; level++) in vlv_compute_wm()
1166 wm_state->sr[level].cursor = in vlv_compute_wm()
1167 wm_state->wm[level].cursor; in vlv_compute_wm()
1170 for (level = 0; level < wm_state->num_levels; level++) in vlv_compute_wm()
1171 wm_state->sr[level].plane = in vlv_compute_wm()
1172 min(wm_state->sr[level].plane, in vlv_compute_wm()
1173 wm_state->wm[level].primary); in vlv_compute_wm()
1177 for (level = 0; level < wm_state->num_levels; level++) in vlv_compute_wm()
1178 wm_state->sr[level].plane = in vlv_compute_wm()
1179 min(wm_state->sr[level].plane, in vlv_compute_wm()
1180 wm_state->wm[level].sprite[sprite]); in vlv_compute_wm()
1186 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { in vlv_compute_wm()
1187 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); in vlv_compute_wm()
1188 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level])); in vlv_compute_wm()
1290 wm->level = to_i915(dev)->wm.max_level; in vlv_merge_wm()
1303 wm->level = min_t(int, wm->level, wm_state->num_levels - 1); in vlv_merge_wm()
1310 wm->level = VLV_WM_LEVEL_PM2; in vlv_merge_wm()
1319 wm->pipe[pipe] = wm_state->wm[wm->level]; in vlv_merge_wm()
1321 wm->sr = wm_state->sr[wm->level]; in vlv_merge_wm()
1347 if (wm.level < VLV_WM_LEVEL_DDR_DVFS && in vlv_update_wm()
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) in vlv_update_wm()
1351 if (wm.level < VLV_WM_LEVEL_PM5 && in vlv_update_wm()
1352 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) in vlv_update_wm()
1367 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); in vlv_update_wm()
1372 if (wm.level >= VLV_WM_LEVEL_PM5 && in vlv_update_wm()
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) in vlv_update_wm()
1376 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS && in vlv_update_wm()
1377 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) in vlv_update_wm()
1866 int level, bool is_sprite) in ilk_plane_wm_reg_max() argument
1870 return level == 0 ? 255 : 2047; in ilk_plane_wm_reg_max()
1873 return level == 0 ? 127 : 1023; in ilk_plane_wm_reg_max()
1876 return level == 0 ? 127 : 511; in ilk_plane_wm_reg_max()
1879 return level == 0 ? 63 : 255; in ilk_plane_wm_reg_max()
1883 int level) in ilk_cursor_wm_reg_max() argument
1886 return level == 0 ? 63 : 255; in ilk_cursor_wm_reg_max()
1888 return level == 0 ? 31 : 63; in ilk_cursor_wm_reg_max()
1901 int level, in ilk_plane_wm_max() argument
1913 if (level == 0 || config->num_pipes_active > 1) { in ilk_plane_wm_max()
1927 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { in ilk_plane_wm_max()
1937 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); in ilk_plane_wm_max()
1942 int level, in ilk_cursor_wm_max() argument
1946 if (level > 0 && config->num_pipes_active > 1) in ilk_cursor_wm_max()
1950 return ilk_cursor_wm_reg_max(dev, level); in ilk_cursor_wm_max()
1954 int level, in ilk_compute_wm_maximums() argument
1959 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); in ilk_compute_wm_maximums()
1960 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); in ilk_compute_wm_maximums()
1961 max->cur = ilk_cursor_wm_max(dev, level, config); in ilk_compute_wm_maximums()
1966 int level, in ilk_compute_wm_reg_maximums() argument
1969 max->pri = ilk_plane_wm_reg_max(dev, level, false); in ilk_compute_wm_reg_maximums()
1970 max->spr = ilk_plane_wm_reg_max(dev, level, true); in ilk_compute_wm_reg_maximums()
1971 max->cur = ilk_cursor_wm_reg_max(dev, level); in ilk_compute_wm_reg_maximums()
1975 static bool ilk_validate_wm_level(int level, in ilk_validate_wm_level() argument
1996 if (level == 0 && !result->enable) { in ilk_validate_wm_level()
1999 level, result->pri_val, max->pri); in ilk_validate_wm_level()
2002 level, result->spr_val, max->spr); in ilk_validate_wm_level()
2005 level, result->cur_val, max->cur); in ilk_validate_wm_level()
2018 int level, in ilk_compute_wm_level() argument
2025 uint16_t pri_latency = dev_priv->wm.pri_latency[level]; in ilk_compute_wm_level()
2026 uint16_t spr_latency = dev_priv->wm.spr_latency[level]; in ilk_compute_wm_level()
2027 uint16_t cur_latency = dev_priv->wm.cur_latency[level]; in ilk_compute_wm_level()
2030 if (level > 0) { in ilk_compute_wm_level()
2038 pri_latency, level); in ilk_compute_wm_level()
2086 int level, max_level = ilk_wm_max_level(dev); in intel_read_wm_latency() local
2134 for (level = 1; level <= max_level; level++) { in intel_read_wm_latency()
2135 if (wm[level] == 0) { in intel_read_wm_latency()
2136 for (i = level + 1; i <= max_level; i++) in intel_read_wm_latency()
2151 for (level = 1; level <= max_level; level++) { in intel_read_wm_latency()
2152 if (wm[level] == 0) in intel_read_wm_latency()
2154 wm[level] += 2; in intel_read_wm_latency()
2220 int level, max_level = ilk_wm_max_level(dev); in intel_print_wm_latency() local
2222 for (level = 0; level <= max_level; level++) { in intel_print_wm_latency()
2223 unsigned int latency = wm[level]; in intel_print_wm_latency()
2227 name, level); in intel_print_wm_latency()
2237 else if (level > 0) in intel_print_wm_latency()
2241 name, level, wm[level], in intel_print_wm_latency()
2249 int level, max_level = ilk_wm_max_level(&dev_priv->drm); in ilk_increase_wm_latency() local
2255 for (level = 1; level <= max_level; level++) in ilk_increase_wm_latency()
2256 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); in ilk_increase_wm_latency()
2348 int level, max_level = ilk_wm_max_level(dev), usable_level; in ilk_compute_pipe_wm() local
2401 for (level = 1; level <= max_level; level++) { in ilk_compute_pipe_wm()
2402 struct intel_wm_level *wm = &pipe_wm->raw_wm[level]; in ilk_compute_pipe_wm()
2404 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, in ilk_compute_pipe_wm()
2412 if (level > usable_level) in ilk_compute_pipe_wm()
2415 if (ilk_validate_wm_level(level, &max, wm)) in ilk_compute_pipe_wm()
2416 pipe_wm->wm[level] = *wm; in ilk_compute_pipe_wm()
2418 usable_level = level; in ilk_compute_pipe_wm()
2435 int level, max_level = ilk_wm_max_level(dev); in ilk_compute_intermediate_wm() local
2447 for (level = 0; level <= max_level; level++) { in ilk_compute_intermediate_wm()
2448 struct intel_wm_level *a_wm = &a->wm[level]; in ilk_compute_intermediate_wm()
2449 const struct intel_wm_level *b_wm = &b->wm[level]; in ilk_compute_intermediate_wm()
2481 int level, in ilk_merge_wm_level() argument
2490 const struct intel_wm_level *wm = &active->wm[level]; in ilk_merge_wm_level()
2519 int level, max_level = ilk_wm_max_level(dev); in ilk_wm_merge() local
2531 for (level = 1; level <= max_level; level++) { in ilk_wm_merge()
2532 struct intel_wm_level *wm = &merged->wm[level]; in ilk_wm_merge()
2534 ilk_merge_wm_level(dev, level, wm); in ilk_wm_merge()
2536 if (level > last_enabled_level) in ilk_wm_merge()
2538 else if (!ilk_validate_wm_level(level, max, wm)) in ilk_wm_merge()
2540 last_enabled_level = level - 1; in ilk_wm_merge()
2561 for (level = 2; level <= max_level; level++) { in ilk_wm_merge()
2562 struct intel_wm_level *wm = &merged->wm[level]; in ilk_wm_merge()
2576 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) in ilk_wm_lp_latency() argument
2581 return 2 * level; in ilk_wm_lp_latency()
2583 return dev_priv->wm.pri_latency[level]; in ilk_wm_lp_latency()
2592 int level, wm_lp; in ilk_compute_wm_results() local
2601 level = ilk_wm_lp_to_level(wm_lp, merged); in ilk_compute_wm_results()
2603 r = &merged->wm[level]; in ilk_compute_wm_results()
2610 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | in ilk_compute_wm_results()
2659 int level, max_level = ilk_wm_max_level(dev); in ilk_find_best_result() local
2662 for (level = 1; level <= max_level; level++) { in ilk_find_best_result()
2663 if (r1->wm[level].enable) in ilk_find_best_result()
2664 level1 = level; in ilk_find_best_result()
2665 if (r2->wm[level].enable) in ilk_find_best_result()
2666 level2 = level; in ilk_find_best_result()
3004 int level, id, latency; in intel_can_enable_sagv() local
3035 for (level = ilk_wm_max_level(dev); in intel_can_enable_sagv()
3036 intel_state->wm_results.plane[pipe][id][level] == 0; --level) in intel_can_enable_sagv()
3039 latency = dev_priv->wm.skl_latency[level]; in intel_can_enable_sagv()
3545 int level, in skl_compute_plane_wm() argument
3552 uint32_t latency = dev_priv->wm.skl_latency[level]; in skl_compute_plane_wm()
3641 if (level >= 1 && level <= 7) { in skl_compute_plane_wm()
3658 if (level) { in skl_compute_plane_wm()
3682 int level, in skl_compute_wm_level() argument
3736 level, in skl_compute_wm_level()
3784 int level, max_level = ilk_wm_max_level(dev); in skl_build_pipe_wm() local
3787 for (level = 0; level <= max_level; level++) { in skl_build_pipe_wm()
3789 level, &pipe_wm->wm[level]); in skl_build_pipe_wm()
3805 int level, max_level = ilk_wm_max_level(dev); in skl_compute_wm_results() local
3810 for (level = 0; level <= max_level; level++) { in skl_compute_wm_results()
3814 temp |= p_wm->wm[level].plane_res_l[i] << in skl_compute_wm_results()
3816 temp |= p_wm->wm[level].plane_res_b[i]; in skl_compute_wm_results()
3817 if (p_wm->wm[level].plane_en[i]) in skl_compute_wm_results()
3820 r->plane[pipe][i][level] = temp; in skl_compute_wm_results()
3825 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; in skl_compute_wm_results()
3826 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR]; in skl_compute_wm_results()
3828 if (p_wm->wm[level].plane_en[PLANE_CURSOR]) in skl_compute_wm_results()
3831 r->plane[pipe][PLANE_CURSOR][level] = temp; in skl_compute_wm_results()
3874 int level, max_level = ilk_wm_max_level(dev); in skl_write_plane_wm() local
3877 for (level = 0; level <= max_level; level++) { in skl_write_plane_wm()
3878 I915_WRITE(PLANE_WM(pipe, plane, level), in skl_write_plane_wm()
3879 wm->plane[pipe][plane][level]); in skl_write_plane_wm()
3895 int level, max_level = ilk_wm_max_level(dev); in skl_write_cursor_wm() local
3898 for (level = 0; level <= max_level; level++) { in skl_write_cursor_wm()
3899 I915_WRITE(CUR_WM(pipe, level), in skl_write_cursor_wm()
3900 wm->plane[pipe][PLANE_CURSOR][level]); in skl_write_cursor_wm()
4303 int level) in skl_pipe_wm_active_state() argument
4309 active->wm[level].plane_en[i] = is_enabled; in skl_pipe_wm_active_state()
4310 active->wm[level].plane_res_b[i] = in skl_pipe_wm_active_state()
4312 active->wm[level].plane_res_l[i] = in skl_pipe_wm_active_state()
4316 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled; in skl_pipe_wm_active_state()
4317 active->wm[level].plane_res_b[PLANE_CURSOR] = in skl_pipe_wm_active_state()
4319 active->wm[level].plane_res_l[PLANE_CURSOR] = in skl_pipe_wm_active_state()
4351 int level, i, max_level; in skl_pipe_wm_get_hw_state() local
4358 for (level = 0; level <= max_level; level++) { in skl_pipe_wm_get_hw_state()
4360 hw->plane[pipe][i][level] = in skl_pipe_wm_get_hw_state()
4361 I915_READ(PLANE_WM(pipe, i, level)); in skl_pipe_wm_get_hw_state()
4362 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level)); in skl_pipe_wm_get_hw_state()
4376 for (level = 0; level <= max_level; level++) { in skl_pipe_wm_get_hw_state()
4378 temp = hw->plane[pipe][i][level]; in skl_pipe_wm_get_hw_state()
4380 false, i, level); in skl_pipe_wm_get_hw_state()
4382 temp = hw->plane[pipe][PLANE_CURSOR][level]; in skl_pipe_wm_get_hw_state()
4383 skl_pipe_wm_active_state(temp, active, false, true, i, level); in skl_pipe_wm_get_hw_state()
4454 int level, max_level = ilk_wm_max_level(dev); in ilk_pipe_wm_get_hw_state() local
4461 for (level = 0; level <= max_level; level++) in ilk_pipe_wm_get_hw_state()
4462 active->wm[level].enable = true; in ilk_pipe_wm_get_hw_state()
4576 wm->level = VLV_WM_LEVEL_PM2; in vlv_wm_get_hw_state()
4583 wm->level = VLV_WM_LEVEL_PM5; in vlv_wm_get_hw_state()
4606 wm->level = VLV_WM_LEVEL_DDR_DVFS; in vlv_wm_get_hw_state()
4618 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); in vlv_wm_get_hw_state()