Lines Matching refs:hdmi_phy
188 static void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, in mtk_hdmi_phy_clear_bits() argument
191 void __iomem *reg = hdmi_phy->regs + offset; in mtk_hdmi_phy_clear_bits()
199 static void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, in mtk_hdmi_phy_set_bits() argument
202 void __iomem *reg = hdmi_phy->regs + offset; in mtk_hdmi_phy_set_bits()
210 static void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset, in mtk_hdmi_phy_mask() argument
213 void __iomem *reg = hdmi_phy->regs + offset; in mtk_hdmi_phy_mask()
228 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); in mtk_hdmi_pll_prepare() local
230 dev_dbg(hdmi_phy->dev, "%s\n", __func__); in mtk_hdmi_pll_prepare()
232 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); in mtk_hdmi_pll_prepare()
233 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); in mtk_hdmi_pll_prepare()
234 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN); in mtk_hdmi_pll_prepare()
235 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); in mtk_hdmi_pll_prepare()
237 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN); in mtk_hdmi_pll_prepare()
239 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); in mtk_hdmi_pll_prepare()
240 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); in mtk_hdmi_pll_prepare()
247 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); in mtk_hdmi_pll_unprepare() local
249 dev_dbg(hdmi_phy->dev, "%s\n", __func__); in mtk_hdmi_pll_unprepare()
251 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); in mtk_hdmi_pll_unprepare()
252 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); in mtk_hdmi_pll_unprepare()
254 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN); in mtk_hdmi_pll_unprepare()
256 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); in mtk_hdmi_pll_unprepare()
257 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); in mtk_hdmi_pll_unprepare()
258 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); in mtk_hdmi_pll_unprepare()
265 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); in mtk_hdmi_pll_set_rate() local
272 dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, in mtk_hdmi_pll_set_rate()
286 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, in mtk_hdmi_pll_set_rate()
288 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); in mtk_hdmi_pll_set_rate()
289 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, in mtk_hdmi_pll_set_rate()
292 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, in mtk_hdmi_pll_set_rate()
294 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, in mtk_hdmi_pll_set_rate()
297 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, in mtk_hdmi_pll_set_rate()
299 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, in mtk_hdmi_pll_set_rate()
305 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, in mtk_hdmi_pll_set_rate()
309 hdmi_ibias = hdmi_phy->ibias; in mtk_hdmi_pll_set_rate()
311 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, in mtk_hdmi_pll_set_rate()
315 hdmi_ibias = hdmi_phy->ibias_up; in mtk_hdmi_pll_set_rate()
317 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, in mtk_hdmi_pll_set_rate()
326 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, in mtk_hdmi_pll_set_rate()
329 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, in mtk_hdmi_pll_set_rate()
330 (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) | in mtk_hdmi_pll_set_rate()
331 (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) | in mtk_hdmi_pll_set_rate()
332 (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) | in mtk_hdmi_pll_set_rate()
333 (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT), in mtk_hdmi_pll_set_rate()
336 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, in mtk_hdmi_pll_set_rate()
351 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); in mtk_hdmi_pll_round_rate() local
353 hdmi_phy->pll_rate = rate; in mtk_hdmi_pll_round_rate()
365 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); in mtk_hdmi_pll_recalc_rate() local
367 return hdmi_phy->pll_rate; in mtk_hdmi_pll_recalc_rate()
378 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) in mtk_hdmi_phy_enable_tmds() argument
380 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, in mtk_hdmi_phy_enable_tmds()
386 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) in mtk_hdmi_phy_disable_tmds() argument
388 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, in mtk_hdmi_phy_disable_tmds()
395 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy); in mtk_hdmi_phy_power_on() local
398 ret = clk_prepare_enable(hdmi_phy->pll); in mtk_hdmi_phy_power_on()
402 mtk_hdmi_phy_enable_tmds(hdmi_phy); in mtk_hdmi_phy_power_on()
409 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy); in mtk_hdmi_phy_power_off() local
411 mtk_hdmi_phy_disable_tmds(hdmi_phy); in mtk_hdmi_phy_power_off()
412 clk_disable_unprepare(hdmi_phy->pll); in mtk_hdmi_phy_power_off()
426 struct mtk_hdmi_phy *hdmi_phy; in mtk_hdmi_phy_probe() local
440 hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL); in mtk_hdmi_phy_probe()
441 if (!hdmi_phy) in mtk_hdmi_phy_probe()
445 hdmi_phy->regs = devm_ioremap_resource(dev, mem); in mtk_hdmi_phy_probe()
446 if (IS_ERR(hdmi_phy->regs)) { in mtk_hdmi_phy_probe()
447 ret = PTR_ERR(hdmi_phy->regs); in mtk_hdmi_phy_probe()
468 hdmi_phy->pll_hw.init = &clk_init; in mtk_hdmi_phy_probe()
469 hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw); in mtk_hdmi_phy_probe()
470 if (IS_ERR(hdmi_phy->pll)) { in mtk_hdmi_phy_probe()
471 ret = PTR_ERR(hdmi_phy->pll); in mtk_hdmi_phy_probe()
477 &hdmi_phy->ibias); in mtk_hdmi_phy_probe()
484 &hdmi_phy->ibias_up); in mtk_hdmi_phy_probe()
491 hdmi_phy->drv_imp_clk = 0x30; in mtk_hdmi_phy_probe()
492 hdmi_phy->drv_imp_d2 = 0x30; in mtk_hdmi_phy_probe()
493 hdmi_phy->drv_imp_d1 = 0x30; in mtk_hdmi_phy_probe()
494 hdmi_phy->drv_imp_d0 = 0x30; in mtk_hdmi_phy_probe()
501 phy_set_drvdata(phy, hdmi_phy); in mtk_hdmi_phy_probe()
507 hdmi_phy->dev = dev; in mtk_hdmi_phy_probe()
509 hdmi_phy->pll); in mtk_hdmi_phy_probe()