974 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }  in REG_A4XX_RB_MRT()
976 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }  in REG_A4XX_RB_MRT_CONTROL()
994 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }  in REG_A4XX_RB_MRT_BUF_INFO()
1027 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }  in REG_A4XX_RB_MRT_BASE()
1029 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }  in REG_A4XX_RB_MRT_CONTROL3()
1037 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }  in REG_A4XX_RB_MRT_BLEND_CONTROL()
1516 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }  in REG_A4XX_RB_VPORT_Z_CLAMP()
1518 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }  in REG_A4XX_RB_VPORT_Z_CLAMP_MIN()
1520 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }  in REG_A4XX_RB_VPORT_Z_CLAMP_MAX()
1526 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_TP()
1528 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_TP_REG()
1530 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL2_TP()
1532 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL2_TP_REG()
1534 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_HYST_TP()
1536 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_HYST_TP_REG()
1538 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_DELAY_TP()
1540 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_DELAY_TP_REG()
1994 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_SP()
1996 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_SP_REG()
1998 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL2_SP()
2000 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL2_SP_REG()
2002 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_HYST_SP()
2004 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_HYST_SP_REG()
2006 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_DELAY_SP()
2008 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_DELAY_SP_REG()
2010 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_RB()
2012 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_RB_REG()
2014 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL2_RB()
2016 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL2_RB_REG()
2018 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU()
2020 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*…  in REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG()
2022 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*…  in REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU()
2024 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + …  in REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG()
2038 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + …  in REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1()
2040 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008…  in REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG()
2182 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }  in REG_A4XX_CP_PROTECT()
2184 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }  in REG_A4XX_CP_PROTECT_REG()
2220 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }  in REG_A4XX_CP_SCRATCH()
2222 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }  in REG_A4XX_CP_SCRATCH_REG()
2330 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }  in REG_A4XX_SP_VS_OUT()
2332 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }  in REG_A4XX_SP_VS_OUT_REG()
2358 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }  in REG_A4XX_SP_VS_VPC_DST()
2360 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }  in REG_A4XX_SP_VS_VPC_DST_REG()
2498 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }  in REG_A4XX_SP_FS_MRT()
2500 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }  in REG_A4XX_SP_FS_MRT_REG()
2566 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }  in REG_A4XX_SP_DS_OUT()
2568 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }  in REG_A4XX_SP_DS_OUT_REG()
2594 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }  in REG_A4XX_SP_DS_VPC_DST()
2596 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }  in REG_A4XX_SP_DS_VPC_DST_REG()
2664 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }  in REG_A4XX_SP_GS_OUT()
2666 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }  in REG_A4XX_SP_GS_OUT_REG()
2692 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }  in REG_A4XX_SP_GS_VPC_DST()
2694 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }  in REG_A4XX_SP_GS_VPC_DST_REG()
2792 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }  in REG_A4XX_VPC_VARYING_INTERP()
2794 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }  in REG_A4XX_VPC_VARYING_INTERP_MODE()
2796 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }  in REG_A4XX_VPC_VARYING_PS_REPL()
2798 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0;…  in REG_A4XX_VPC_VARYING_PS_REPL_MODE()
2822 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }  in REG_A4XX_VSC_PIPE_CONFIG()
2824 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }  in REG_A4XX_VSC_PIPE_CONFIG_REG()
2850 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }  in REG_A4XX_VSC_PIPE_DATA_ADDRESS()
2852 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0…  in REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG()
2854 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }  in REG_A4XX_VSC_PIPE_DATA_LENGTH()
2856 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0;…  in REG_A4XX_VSC_PIPE_DATA_LENGTH_REG()
2958 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }  in REG_A4XX_VFD_FETCH()
2960 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }  in REG_A4XX_VFD_FETCH_INSTR_0()
2976 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }  in REG_A4XX_VFD_FETCH_INSTR_1()
2978 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }  in REG_A4XX_VFD_FETCH_INSTR_2()
2986 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }  in REG_A4XX_VFD_FETCH_INSTR_3()
2994 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }  in REG_A4XX_VFD_DECODE()
2996 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }  in REG_A4XX_VFD_DECODE_INSTR()