Lines Matching refs:DBG
114 DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* "); in pll_28nm_poll_for_ready()
182 DBG("refclk_cfg = %d", refclk_cfg); in dsi_pll_28nm_clk_set_rate()
187 DBG("div_fb = %lu", div_fbx1000); in dsi_pll_28nm_clk_set_rate()
188 DBG("frac_n_value = %d", frac_n_value); in dsi_pll_28nm_clk_set_rate()
190 DBG("Generated VCO Clock: %lu", gen_vco_clk); in dsi_pll_28nm_clk_set_rate()
210 DBG("sdm_cfg0=%d", sdm_cfg0); in dsi_pll_28nm_clk_set_rate()
211 DBG("sdm_cfg1=%d", sdm_cfg1); in dsi_pll_28nm_clk_set_rate()
212 DBG("sdm_cfg2=%d", sdm_cfg2); in dsi_pll_28nm_clk_set_rate()
213 DBG("sdm_cfg3=%d", sdm_cfg3); in dsi_pll_28nm_clk_set_rate()
217 DBG("cal_cfg10=%d, cal_cfg11=%d", cal_cfg10, cal_cfg11); in dsi_pll_28nm_clk_set_rate()
291 DBG("sdm_dc_off = %d", sdm_dc_off); in dsi_pll_28nm_clk_recalc_rate()
297 DBG("sdm_freq_seed = %d", sdm_freq_seed); in dsi_pll_28nm_clk_recalc_rate()
301 DBG("vco rate = %lu", vco_rate); in dsi_pll_28nm_clk_recalc_rate()
304 DBG("returning vco rate = %lu", vco_rate); in dsi_pll_28nm_clk_recalc_rate()
331 DBG("id=%d", pll_28nm->id); in dsi_pll_28nm_enable_seq_hpm()
391 DBG("DSI PLL Lock success"); in dsi_pll_28nm_enable_seq_hpm()
405 DBG("id=%d", pll_28nm->id); in dsi_pll_28nm_enable_seq_lp()
434 DBG("DSI PLL lock success"); in dsi_pll_28nm_enable_seq_lp()
443 DBG("id=%d", pll_28nm->id); in dsi_pll_28nm_disable_seq()
533 DBG("%d", pll_28nm->id); in pll_28nm_register()