Lines Matching refs:head
39 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value) in NVWriteVgaSeq() argument
41 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); in NVWriteVgaSeq()
42 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value); in NVWriteVgaSeq()
46 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index) in NVReadVgaSeq() argument
48 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); in NVReadVgaSeq()
49 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR); in NVReadVgaSeq()
53 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value) in NVWriteVgaGr() argument
55 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); in NVWriteVgaGr()
56 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value); in NVWriteVgaGr()
60 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index) in NVReadVgaGr() argument
62 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); in NVReadVgaGr()
63 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX); in NVReadVgaGr()
110 NVBlankScreen(struct drm_device *dev, int head, bool blank) in NVBlankScreen() argument
115 NVSetOwner(dev, head); in NVBlankScreen()
117 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); in NVBlankScreen()
119 NVVgaSeqReset(dev, head, true); in NVBlankScreen()
121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); in NVBlankScreen()
123 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); in NVBlankScreen()
124 NVVgaSeqReset(dev, head, false); in NVBlankScreen()
247 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) in nouveau_hw_fix_bad_vpll() argument
261 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; in nouveau_hw_fix_bad_vpll()
272 NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1); in nouveau_hw_fix_bad_vpll()
374 rd_cio_state(struct drm_device *dev, int head, in rd_cio_state() argument
377 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); in rd_cio_state()
381 wr_cio_state(struct drm_device *dev, int head, in wr_cio_state() argument
384 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); in wr_cio_state()
388 nv_save_state_ramdac(struct drm_device *dev, int head, in nv_save_state_ramdac() argument
392 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_save_state_ramdac()
396 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); in nv_save_state_ramdac()
398 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); in nv_save_state_ramdac()
403 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); in nv_save_state_ramdac()
405 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); in nv_save_state_ramdac()
408 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); in nv_save_state_ramdac()
410 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); in nv_save_state_ramdac()
412 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); in nv_save_state_ramdac()
413 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); in nv_save_state_ramdac()
414 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); in nv_save_state_ramdac()
415 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); in nv_save_state_ramdac()
416 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); in nv_save_state_ramdac()
417 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); in nv_save_state_ramdac()
418 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); in nv_save_state_ramdac()
419 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); in nv_save_state_ramdac()
423 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); in nv_save_state_ramdac()
424 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); in nv_save_state_ramdac()
428 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); in nv_save_state_ramdac()
430 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); in nv_save_state_ramdac()
431 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); in nv_save_state_ramdac()
435 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); in nv_save_state_ramdac()
436 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); in nv_save_state_ramdac()
437 if (!nv_gf4_disp_arch(dev) && head == 0) { in nv_save_state_ramdac()
443 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); in nv_save_state_ramdac()
444 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); in nv_save_state_ramdac()
446 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); in nv_save_state_ramdac()
449 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); in nv_save_state_ramdac()
452 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); in nv_save_state_ramdac()
453 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); in nv_save_state_ramdac()
454 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); in nv_save_state_ramdac()
457 regp->ctv_regs[i] = NVReadRAMDAC(dev, head, in nv_save_state_ramdac()
463 nv_load_state_ramdac(struct drm_device *dev, int head, in nv_load_state_ramdac() argument
468 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_load_state_ramdac()
469 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; in nv_load_state_ramdac()
473 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); in nv_load_state_ramdac()
480 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); in nv_load_state_ramdac()
482 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); in nv_load_state_ramdac()
485 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); in nv_load_state_ramdac()
487 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); in nv_load_state_ramdac()
489 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); in nv_load_state_ramdac()
490 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); in nv_load_state_ramdac()
491 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); in nv_load_state_ramdac()
492 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); in nv_load_state_ramdac()
493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); in nv_load_state_ramdac()
494 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); in nv_load_state_ramdac()
495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); in nv_load_state_ramdac()
496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); in nv_load_state_ramdac()
501 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); in nv_load_state_ramdac()
502 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); in nv_load_state_ramdac()
506 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); in nv_load_state_ramdac()
508 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); in nv_load_state_ramdac()
509 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); in nv_load_state_ramdac()
513 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); in nv_load_state_ramdac()
514 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); in nv_load_state_ramdac()
515 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); in nv_load_state_ramdac()
516 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); in nv_load_state_ramdac()
518 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); in nv_load_state_ramdac()
521 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); in nv_load_state_ramdac()
524 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); in nv_load_state_ramdac()
525 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); in nv_load_state_ramdac()
526 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); in nv_load_state_ramdac()
529 NVWriteRAMDAC(dev, head, in nv_load_state_ramdac()
535 nv_save_state_vga(struct drm_device *dev, int head, in nv_save_state_vga() argument
538 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_save_state_vga()
541 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); in nv_save_state_vga()
544 rd_cio_state(dev, head, regp, i); in nv_save_state_vga()
546 NVSetEnablePalette(dev, head, true); in nv_save_state_vga()
548 regp->Attribute[i] = NVReadVgaAttr(dev, head, i); in nv_save_state_vga()
549 NVSetEnablePalette(dev, head, false); in nv_save_state_vga()
552 regp->Graphics[i] = NVReadVgaGr(dev, head, i); in nv_save_state_vga()
555 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); in nv_save_state_vga()
559 nv_load_state_vga(struct drm_device *dev, int head, in nv_load_state_vga() argument
562 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_load_state_vga()
565 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); in nv_load_state_vga()
568 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); in nv_load_state_vga()
570 nv_lock_vga_crtc_base(dev, head, false); in nv_load_state_vga()
572 wr_cio_state(dev, head, regp, i); in nv_load_state_vga()
573 nv_lock_vga_crtc_base(dev, head, true); in nv_load_state_vga()
576 NVWriteVgaGr(dev, head, i, regp->Graphics[i]); in nv_load_state_vga()
578 NVSetEnablePalette(dev, head, true); in nv_load_state_vga()
580 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); in nv_load_state_vga()
581 NVSetEnablePalette(dev, head, false); in nv_load_state_vga()
585 nv_save_state_ext(struct drm_device *dev, int head, in nv_save_state_ext() argument
589 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_save_state_ext()
592 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); in nv_save_state_ext()
593 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); in nv_save_state_ext()
594 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); in nv_save_state_ext()
595 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); in nv_save_state_ext()
596 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); in nv_save_state_ext()
597 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); in nv_save_state_ext()
598 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); in nv_save_state_ext()
600 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); in nv_save_state_ext()
601 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); in nv_save_state_ext()
602 rd_cio_state(dev, head, regp, NV_CIO_CRE_21); in nv_save_state_ext()
605 rd_cio_state(dev, head, regp, NV_CIO_CRE_47); in nv_save_state_ext()
608 rd_cio_state(dev, head, regp, 0x9f); in nv_save_state_ext()
610 rd_cio_state(dev, head, regp, NV_CIO_CRE_49); in nv_save_state_ext()
611 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); in nv_save_state_ext()
612 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); in nv_save_state_ext()
613 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); in nv_save_state_ext()
614 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); in nv_save_state_ext()
617 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); in nv_save_state_ext()
618 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); in nv_save_state_ext()
621 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); in nv_save_state_ext()
624 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); in nv_save_state_ext()
627 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); in nv_save_state_ext()
628 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); in nv_save_state_ext()
631 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); in nv_save_state_ext()
633 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); in nv_save_state_ext()
634 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); in nv_save_state_ext()
636 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); in nv_save_state_ext()
637 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); in nv_save_state_ext()
638 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); in nv_save_state_ext()
639 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); in nv_save_state_ext()
643 rd_cio_state(dev, head, regp, NV_CIO_CRE_42); in nv_save_state_ext()
644 rd_cio_state(dev, head, regp, NV_CIO_CRE_53); in nv_save_state_ext()
645 rd_cio_state(dev, head, regp, NV_CIO_CRE_54); in nv_save_state_ext()
648 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); in nv_save_state_ext()
649 rd_cio_state(dev, head, regp, NV_CIO_CRE_59); in nv_save_state_ext()
650 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); in nv_save_state_ext()
652 rd_cio_state(dev, head, regp, NV_CIO_CRE_85); in nv_save_state_ext()
653 rd_cio_state(dev, head, regp, NV_CIO_CRE_86); in nv_save_state_ext()
656 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); in nv_save_state_ext()
660 nv_load_state_ext(struct drm_device *dev, int head, in nv_load_state_ext() argument
665 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_load_state_ext()
675 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); in nv_load_state_ext()
687 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); in nv_load_state_ext()
688 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); in nv_load_state_ext()
689 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); in nv_load_state_ext()
692 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); in nv_load_state_ext()
695 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); in nv_load_state_ext()
697 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); in nv_load_state_ext()
699 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000); in nv_load_state_ext()
701 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000); in nv_load_state_ext()
705 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); in nv_load_state_ext()
707 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); in nv_load_state_ext()
708 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); in nv_load_state_ext()
709 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); in nv_load_state_ext()
710 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); in nv_load_state_ext()
711 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); in nv_load_state_ext()
712 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); in nv_load_state_ext()
713 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); in nv_load_state_ext()
714 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); in nv_load_state_ext()
715 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); in nv_load_state_ext()
718 wr_cio_state(dev, head, regp, NV_CIO_CRE_47); in nv_load_state_ext()
721 wr_cio_state(dev, head, regp, 0x9f); in nv_load_state_ext()
723 wr_cio_state(dev, head, regp, NV_CIO_CRE_49); in nv_load_state_ext()
724 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); in nv_load_state_ext()
725 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); in nv_load_state_ext()
726 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); in nv_load_state_ext()
728 nv_fix_nv40_hw_cursor(dev, head); in nv_load_state_ext()
729 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); in nv_load_state_ext()
731 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); in nv_load_state_ext()
732 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); in nv_load_state_ext()
734 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); in nv_load_state_ext()
735 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); in nv_load_state_ext()
736 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); in nv_load_state_ext()
737 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); in nv_load_state_ext()
754 wr_cio_state(dev, head, regp, NV_CIO_CRE_42); in nv_load_state_ext()
755 wr_cio_state(dev, head, regp, NV_CIO_CRE_53); in nv_load_state_ext()
756 wr_cio_state(dev, head, regp, NV_CIO_CRE_54); in nv_load_state_ext()
759 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); in nv_load_state_ext()
760 wr_cio_state(dev, head, regp, NV_CIO_CRE_59); in nv_load_state_ext()
761 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); in nv_load_state_ext()
763 wr_cio_state(dev, head, regp, NV_CIO_CRE_85); in nv_load_state_ext()
764 wr_cio_state(dev, head, regp, NV_CIO_CRE_86); in nv_load_state_ext()
767 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); in nv_load_state_ext()
771 nv_save_state_palette(struct drm_device *dev, int head, in nv_save_state_palette() argument
775 int head_offset = head * NV_PRMDIO_SIZE, i; in nv_save_state_palette()
782 state->crtc_reg[head].DAC[i] = nvif_rd08(device, in nv_save_state_palette()
786 NVSetEnablePalette(dev, head, false); in nv_save_state_palette()
790 nouveau_hw_load_state_palette(struct drm_device *dev, int head, in nouveau_hw_load_state_palette() argument
794 int head_offset = head * NV_PRMDIO_SIZE, i; in nouveau_hw_load_state_palette()
802 state->crtc_reg[head].DAC[i]); in nouveau_hw_load_state_palette()
805 NVSetEnablePalette(dev, head, false); in nouveau_hw_load_state_palette()
808 void nouveau_hw_save_state(struct drm_device *dev, int head, in nouveau_hw_save_state() argument
815 nouveau_hw_fix_bad_vpll(dev, head); in nouveau_hw_save_state()
816 nv_save_state_ramdac(dev, head, state); in nouveau_hw_save_state()
817 nv_save_state_vga(dev, head, state); in nouveau_hw_save_state()
818 nv_save_state_palette(dev, head, state); in nouveau_hw_save_state()
819 nv_save_state_ext(dev, head, state); in nouveau_hw_save_state()
822 void nouveau_hw_load_state(struct drm_device *dev, int head, in nouveau_hw_load_state() argument
825 NVVgaProtect(dev, head, true); in nouveau_hw_load_state()
826 nv_load_state_ramdac(dev, head, state); in nouveau_hw_load_state()
827 nv_load_state_ext(dev, head, state); in nouveau_hw_load_state()
828 nouveau_hw_load_state_palette(dev, head, state); in nouveau_hw_load_state()
829 nv_load_state_vga(dev, head, state); in nouveau_hw_load_state()
830 NVVgaProtect(dev, head, false); in nouveau_hw_load_state()