Lines Matching refs:r5
200 mov $r5 0x114
201 iowrs I[$r15] $r5
204 shl b32 $r5 $r3 4
205 add b32 $r5 2
206 mov $xdbase $r5
207 mov $r5 $sp
209 sub b32 $r5 0x100
212 and $r5 $r6
213 sethi $r5 0x00020000
214 xdld $r4 $r5
216 sethi $r5 0
221 ld b32 $r4 D[$r5 + 0]
223 ld b32 $r6 D[$r5 + 4]
269 mov $r5 #ctx_dma
272 ld b32 $r7 D[$r5 + $r6 * 4]
294 mov $r5 #dispatch_table
298 ld b16 $r6 D[$r5 + 0]
299 ld b16 $r7 D[$r5 + 2]
300 add b32 $r5 4
308 add b32 $r5 $r7
315 add b32 $r4 $r5
316 ld b32 $r5 D[$r4 + 4]
317 and $r5 $r3
318 cmpu b32 $r5 0
322 ld b16 $r5 D[$r4 + 0]
326 st b32 D[$r5] $r3
330 call $r5
428 extr $r5 $r4 16:17
429 add b32 $r5 1
446 mulu $r12 $r10 $r5
467 cmpu b32 $r11 $r5
474 mulu $r6 $r5
482 mulu $r7 $r5
486 mov $r5 0x810
487 shl b32 $r5 6
488 iowr I[$r5 + 0x000] $r6
489 iowr I[$r5 + 0x100] $r7
490 add b32 $r5 0x800
497 iowr I[$r5 + 0x000] $r6
498 add b32 $r5 0x100
500 iowr I[$r5 + 0x000] $r6
502 iowr I[$r5 + 0x100] $r6
504 iowr I[$r5 + 0x200] $r6
506 iowr I[$r5 + 0x300] $r6
507 add b32 $r5 0x400
509 iowr I[$r5 + 0x000] $r6
511 iowr I[$r5 + 0x100] $r6
535 // $r5: ctx offset adjustment for src/dst selection
540 ld b32 $r7 D[$r5 + #ctx_src_tile_mode]
562 ld b32 $r10 D[$r5 + #ctx_src_xoff]
563 ld b32 $r11 D[$r5 + #ctx_src_cpp]
573 ld b32 $r13 D[$r5 + #ctx_src_yoff]
595 ld b32 $r15 D[$r5 + #ctx_src_xsize]
596 ld b32 $r11 D[$r5 + #ctx_src_cpp]
606 ld b32 $r15 D[$r5 + #ctx_src_ysize]
626 ld b32 $r8 D[$r5 + #ctx_src_zoff]
653 ld b32 $r7 D[$r5 + #ctx_src_address_low]
654 ld b32 $r8 D[$r5 + #ctx_src_address_high]
674 ld b32 $r7 D[$r5 + #ctx_src_address_low]
677 ld b32 $r7 D[$r5 + #ctx_src_address_high]
681 ld b32 $r7 D[$r5 + #ctx_src_pitch]
706 ld b32 $r5 D[$r0 + #ctx_query_address_low]
707 add b32 $r5 4
708 iowr I[$r4 + 0x000] $r5
710 mov $r5 0xc
711 iowr I[$r4 + 0x200] $r5
713 ld b32 $r5 D[$r0 + #ctx_query_address_high]
714 shl b32 $r5 16
715 iowr I[$r4 + 0x000] $r5
717 mov $r5 0x00000b00
718 sethi $r5 0x00010000
719 iowr I[$r4 + 0x000] $r5
720 mov $r5 0x00004040
721 shl b32 $r5 1
722 sethi $r5 0x80800000
723 iowr I[$r4 + 0x100] $r5
724 mov $r5 0x00001110
725 sethi $r5 0x13120000
726 iowr I[$r4 + 0x200] $r5
727 mov $r5 0x00001514
728 sethi $r5 0x17160000
729 iowr I[$r4 + 0x300] $r5
730 mov $r5 0x00002601
731 sethi $r5 0x00010000
734 iowr I[$r4 + 0x000] $r5
741 ld b32 $r5 D[$r0 + #ctx_query_address_low]
742 iowr I[$r4 + 0x000] $r5
744 mov $r5 0x4
745 iowr I[$r4 + 0x200] $r5
747 ld b32 $r5 D[$r0 + #ctx_query_address_high]
748 shl b32 $r5 16
749 iowr I[$r4 + 0x000] $r5
751 mov $r5 0x00000300
752 iowr I[$r4 + 0x000] $r5
753 mov $r5 0x00001110
754 sethi $r5 0x13120000
755 iowr I[$r4 + 0x100] $r5
756 ld b32 $r5 D[$r0 + #ctx_query_counter]
758 iowr I[$r4 + 0x000] $r5
759 mov $r5 0x00002601
760 sethi $r5 0x00010000
763 iowr I[$r4 + 0x000] $r5
806 clear b32 $r5
817 mov $r5 #ctx_dst_address_high - #ctx_src_address_high
827 mov $r5 0x800
828 shl b32 $r5 6
830 iowr I[$r5 + 0x100] $r6
835 iowr I[$r5] $r4