2626 	pi->dpm_level_enable_mask.pcie_dpm_enable_mask =  in ci_populate_smc_link_level()
3287 	pi->dpm_level_enable_mask.sclk_dpm_enable_mask =  in ci_populate_all_graphic_levels()
3341 	pi->dpm_level_enable_mask.mclk_dpm_enable_mask =  in ci_populate_all_memory_levels()
3805 		if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {  in ci_upload_dpm_level_enable_mask()
3808 								   pi->dpm_level_enable_mask.sclk_dpm_enable_mask);  in ci_upload_dpm_level_enable_mask()
3815 		if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {  in ci_upload_dpm_level_enable_mask()
3818 								   pi->dpm_level_enable_mask.mclk_dpm_enable_mask);  in ci_upload_dpm_level_enable_mask()
3825 		if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {  in ci_upload_dpm_level_enable_mask()
3828 								   pi->dpm_level_enable_mask.pcie_dpm_enable_mask);  in ci_upload_dpm_level_enable_mask()
3925 		pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;  in ci_enable_uvd_dpm()
3929 				pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;  in ci_enable_uvd_dpm()
3938 						  pi->dpm_level_enable_mask.uvd_dpm_enable_mask);  in ci_enable_uvd_dpm()
3942 			pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;  in ci_enable_uvd_dpm()
3945 							  pi->dpm_level_enable_mask.mclk_dpm_enable_mask);  in ci_enable_uvd_dpm()
3950 			pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;  in ci_enable_uvd_dpm()
3953 							  pi->dpm_level_enable_mask.mclk_dpm_enable_mask);  in ci_enable_uvd_dpm()
3974 		pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;  in ci_enable_vce_dpm()
3977 				pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;  in ci_enable_vce_dpm()
3986 						  pi->dpm_level_enable_mask.vce_dpm_enable_mask);  in ci_enable_vce_dpm()
4007 		pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4010 				pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4019 						  pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4038 		pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4041 				pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4050 						  pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4160 	pi->dpm_level_enable_mask.sclk_dpm_enable_mask =  in ci_generate_dpm_level_enable_mask()
4162 	pi->dpm_level_enable_mask.mclk_dpm_enable_mask =  in ci_generate_dpm_level_enable_mask()
4165 		pi->dpm_level_enable_mask.mclk_dpm_enable_mask;  in ci_generate_dpm_level_enable_mask()
4167 		if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)  in ci_generate_dpm_level_enable_mask()
4168 			pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;  in ci_generate_dpm_level_enable_mask()
4170 	pi->dpm_level_enable_mask.pcie_dpm_enable_mask =  in ci_generate_dpm_level_enable_mask()
4197 		    pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {  in ci_dpm_force_performance_level()
4199 			tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;  in ci_dpm_force_performance_level()
4216 		    pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {  in ci_dpm_force_performance_level()
4218 			tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;  in ci_dpm_force_performance_level()
4235 		    pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {  in ci_dpm_force_performance_level()
4237 			tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;  in ci_dpm_force_performance_level()
4255 		    pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {  in ci_dpm_force_performance_level()
4257 							     pi->dpm_level_enable_mask.sclk_dpm_enable_mask);  in ci_dpm_force_performance_level()
4270 		    pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {  in ci_dpm_force_performance_level()
4272 							     pi->dpm_level_enable_mask.mclk_dpm_enable_mask);  in ci_dpm_force_performance_level()
4285 		    pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {  in ci_dpm_force_performance_level()
4287 							     pi->dpm_level_enable_mask.pcie_dpm_enable_mask);  in ci_dpm_force_performance_level()