Lines Matching refs:table
1308 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits() local
1314 table->FpsHighT = cpu_to_be16(tmp); in ci_init_fps_limits()
1317 table->FpsLowT = cpu_to_be16(tmp); in ci_init_fps_limits()
2201 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vddc_table() argument
2206 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2207 for (count = 0; count < table->VddcLevelCount; count++) { in ci_populate_smc_vddc_table()
2210 &table->VddcLevel[count]); in ci_populate_smc_vddc_table()
2213 table->VddcLevel[count].Smio |= in ci_populate_smc_vddc_table()
2216 table->VddcLevel[count].Smio = 0; in ci_populate_smc_vddc_table()
2218 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); in ci_populate_smc_vddc_table()
2224 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vddci_table() argument
2229 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2230 for (count = 0; count < table->VddciLevelCount; count++) { in ci_populate_smc_vddci_table()
2233 &table->VddciLevel[count]); in ci_populate_smc_vddci_table()
2236 table->VddciLevel[count].Smio |= in ci_populate_smc_vddci_table()
2239 table->VddciLevel[count].Smio = 0; in ci_populate_smc_vddci_table()
2241 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); in ci_populate_smc_vddci_table()
2247 SMU7_Discrete_DpmTable *table) in ci_populate_smc_mvdd_table() argument
2252 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2253 for (count = 0; count < table->MvddLevelCount; count++) { in ci_populate_smc_mvdd_table()
2256 &table->MvddLevel[count]); in ci_populate_smc_mvdd_table()
2259 table->MvddLevel[count].Smio |= in ci_populate_smc_mvdd_table()
2262 table->MvddLevel[count].Smio = 0; in ci_populate_smc_mvdd_table()
2264 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); in ci_populate_smc_mvdd_table()
2270 SMU7_Discrete_DpmTable *table) in ci_populate_smc_voltage_tables() argument
2274 ret = ci_populate_smc_vddc_table(rdev, table); in ci_populate_smc_voltage_tables()
2278 ret = ci_populate_smc_vddci_table(rdev, table); in ci_populate_smc_voltage_tables()
2282 ret = ci_populate_smc_mvdd_table(rdev, table); in ci_populate_smc_voltage_tables()
2609 SMU7_Discrete_DpmTable *table) in ci_populate_smc_link_level() argument
2616 table->LinkLevel[i].PcieGenSpeed = in ci_populate_smc_link_level()
2618 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
2620 table->LinkLevel[i].EnabledForActivity = 1; in ci_populate_smc_link_level()
2621 table->LinkLevel[i].DownT = cpu_to_be32(5); in ci_populate_smc_link_level()
2622 table->LinkLevel[i].UpT = cpu_to_be32(30); in ci_populate_smc_link_level()
2631 SMU7_Discrete_DpmTable *table) in ci_populate_smc_uvd_level() argument
2637 table->UvdLevelCount = in ci_populate_smc_uvd_level()
2640 for (count = 0; count < table->UvdLevelCount; count++) { in ci_populate_smc_uvd_level()
2641 table->UvdLevel[count].VclkFrequency = in ci_populate_smc_uvd_level()
2643 table->UvdLevel[count].DclkFrequency = in ci_populate_smc_uvd_level()
2645 table->UvdLevel[count].MinVddc = in ci_populate_smc_uvd_level()
2647 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()
2651 table->UvdLevel[count].VclkFrequency, false, ÷rs); in ci_populate_smc_uvd_level()
2655 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2659 table->UvdLevel[count].DclkFrequency, false, ÷rs); in ci_populate_smc_uvd_level()
2663 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2665 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); in ci_populate_smc_uvd_level()
2666 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); in ci_populate_smc_uvd_level()
2667 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); in ci_populate_smc_uvd_level()
2674 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vce_level() argument
2680 table->VceLevelCount = in ci_populate_smc_vce_level()
2683 for (count = 0; count < table->VceLevelCount; count++) { in ci_populate_smc_vce_level()
2684 table->VceLevel[count].Frequency = in ci_populate_smc_vce_level()
2686 table->VceLevel[count].MinVoltage = in ci_populate_smc_vce_level()
2688 table->VceLevel[count].MinPhases = 1; in ci_populate_smc_vce_level()
2692 table->VceLevel[count].Frequency, false, ÷rs); in ci_populate_smc_vce_level()
2696 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2698 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); in ci_populate_smc_vce_level()
2699 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); in ci_populate_smc_vce_level()
2707 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acp_level() argument
2713 table->AcpLevelCount = (u8) in ci_populate_smc_acp_level()
2716 for (count = 0; count < table->AcpLevelCount; count++) { in ci_populate_smc_acp_level()
2717 table->AcpLevel[count].Frequency = in ci_populate_smc_acp_level()
2719 table->AcpLevel[count].MinVoltage = in ci_populate_smc_acp_level()
2721 table->AcpLevel[count].MinPhases = 1; in ci_populate_smc_acp_level()
2725 table->AcpLevel[count].Frequency, false, ÷rs); in ci_populate_smc_acp_level()
2729 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()
2731 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); in ci_populate_smc_acp_level()
2732 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); in ci_populate_smc_acp_level()
2739 SMU7_Discrete_DpmTable *table) in ci_populate_smc_samu_level() argument
2745 table->SamuLevelCount = in ci_populate_smc_samu_level()
2748 for (count = 0; count < table->SamuLevelCount; count++) { in ci_populate_smc_samu_level()
2749 table->SamuLevel[count].Frequency = in ci_populate_smc_samu_level()
2751 table->SamuLevel[count].MinVoltage = in ci_populate_smc_samu_level()
2753 table->SamuLevel[count].MinPhases = 1; in ci_populate_smc_samu_level()
2757 table->SamuLevel[count].Frequency, false, ÷rs); in ci_populate_smc_samu_level()
2761 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
2763 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); in ci_populate_smc_samu_level()
2764 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); in ci_populate_smc_samu_level()
2972 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acpi_level() argument
2983 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; in ci_populate_smc_acpi_level()
2986 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2988 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2990 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
2992 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; in ci_populate_smc_acpi_level()
2996 table->ACPILevel.SclkFrequency, false, ÷rs); in ci_populate_smc_acpi_level()
3000 table->ACPILevel.SclkDid = (u8)dividers.post_divider; in ci_populate_smc_acpi_level()
3001 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; in ci_populate_smc_acpi_level()
3002 table->ACPILevel.DeepSleepDivId = 0; in ci_populate_smc_acpi_level()
3010 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; in ci_populate_smc_acpi_level()
3011 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; in ci_populate_smc_acpi_level()
3012 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
3013 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
3014 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
3015 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3016 table->ACPILevel.CcPwrDynRm = 0; in ci_populate_smc_acpi_level()
3017 table->ACPILevel.CcPwrDynRm1 = 0; in ci_populate_smc_acpi_level()
3019 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); in ci_populate_smc_acpi_level()
3020 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); in ci_populate_smc_acpi_level()
3021 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); in ci_populate_smc_acpi_level()
3022 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); in ci_populate_smc_acpi_level()
3023 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); in ci_populate_smc_acpi_level()
3024 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); in ci_populate_smc_acpi_level()
3025 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); in ci_populate_smc_acpi_level()
3026 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); in ci_populate_smc_acpi_level()
3027 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); in ci_populate_smc_acpi_level()
3028 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); in ci_populate_smc_acpi_level()
3029 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); in ci_populate_smc_acpi_level()
3031 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; in ci_populate_smc_acpi_level()
3032 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in ci_populate_smc_acpi_level()
3036 table->MemoryACPILevel.MinVddci = in ci_populate_smc_acpi_level()
3039 table->MemoryACPILevel.MinVddci = in ci_populate_smc_acpi_level()
3044 table->MemoryACPILevel.MinMvdd = 0; in ci_populate_smc_acpi_level()
3046 table->MemoryACPILevel.MinMvdd = in ci_populate_smc_acpi_level()
3054 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); in ci_populate_smc_acpi_level()
3055 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); in ci_populate_smc_acpi_level()
3056 table->MemoryACPILevel.MpllAdFuncCntl = in ci_populate_smc_acpi_level()
3058 table->MemoryACPILevel.MpllDqFuncCntl = in ci_populate_smc_acpi_level()
3060 table->MemoryACPILevel.MpllFuncCntl = in ci_populate_smc_acpi_level()
3062 table->MemoryACPILevel.MpllFuncCntl_1 = in ci_populate_smc_acpi_level()
3064 table->MemoryACPILevel.MpllFuncCntl_2 = in ci_populate_smc_acpi_level()
3066 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3067 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3069 table->MemoryACPILevel.EnabledForThrottle = 0; in ci_populate_smc_acpi_level()
3070 table->MemoryACPILevel.EnabledForActivity = 0; in ci_populate_smc_acpi_level()
3071 table->MemoryACPILevel.UpH = 0; in ci_populate_smc_acpi_level()
3072 table->MemoryACPILevel.DownH = 100; in ci_populate_smc_acpi_level()
3073 table->MemoryACPILevel.VoltageDownH = 0; in ci_populate_smc_acpi_level()
3074 table->MemoryACPILevel.ActivityLevel = in ci_populate_smc_acpi_level()
3077 table->MemoryACPILevel.StutterEnable = false; in ci_populate_smc_acpi_level()
3078 table->MemoryACPILevel.StrobeEnable = false; in ci_populate_smc_acpi_level()
3079 table->MemoryACPILevel.EdcReadEnable = false; in ci_populate_smc_acpi_level()
3080 table->MemoryACPILevel.EdcWriteEnable = false; in ci_populate_smc_acpi_level()
3081 table->MemoryACPILevel.RttEnable = false; in ci_populate_smc_acpi_level()
3521 static int ci_find_boot_level(struct ci_single_dpm_table *table, in ci_find_boot_level() argument
3527 for(i = 0; i < table->count; i++) { in ci_find_boot_level()
3528 if (value == table->dpm_levels[i].value) { in ci_find_boot_level()
3542 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table() local
3550 ci_populate_smc_voltage_tables(rdev, table); in ci_init_smc_table()
3555 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; in ci_init_smc_table()
3558 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; in ci_init_smc_table()
3561 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; in ci_init_smc_table()
3578 ci_populate_smc_link_level(rdev, table); in ci_init_smc_table()
3580 ret = ci_populate_smc_acpi_level(rdev, table); in ci_init_smc_table()
3584 ret = ci_populate_smc_vce_level(rdev, table); in ci_init_smc_table()
3588 ret = ci_populate_smc_acp_level(rdev, table); in ci_init_smc_table()
3592 ret = ci_populate_smc_samu_level(rdev, table); in ci_init_smc_table()
3600 ret = ci_populate_smc_uvd_level(rdev, table); in ci_init_smc_table()
3604 table->UvdBootLevel = 0; in ci_init_smc_table()
3605 table->VceBootLevel = 0; in ci_init_smc_table()
3606 table->AcpBootLevel = 0; in ci_init_smc_table()
3607 table->SamuBootLevel = 0; in ci_init_smc_table()
3608 table->GraphicsBootLevel = 0; in ci_init_smc_table()
3609 table->MemoryBootLevel = 0; in ci_init_smc_table()
3619 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3620 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3621 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3629 table->UVDInterval = 1; in ci_init_smc_table()
3630 table->VCEInterval = 1; in ci_init_smc_table()
3631 table->ACPInterval = 1; in ci_init_smc_table()
3632 table->SAMUInterval = 1; in ci_init_smc_table()
3633 table->GraphicsVoltageChangeEnable = 1; in ci_init_smc_table()
3634 table->GraphicsThermThrottleEnable = 1; in ci_init_smc_table()
3635 table->GraphicsInterval = 1; in ci_init_smc_table()
3636 table->VoltageInterval = 1; in ci_init_smc_table()
3637 table->ThermalInterval = 1; in ci_init_smc_table()
3638 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3640 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3642 table->MemoryVoltageChangeEnable = 1; in ci_init_smc_table()
3643 table->MemoryInterval = 1; in ci_init_smc_table()
3644 table->VoltageResponseTime = 0; in ci_init_smc_table()
3645 table->VddcVddciDelta = 4000; in ci_init_smc_table()
3646 table->PhaseResponseTime = 0; in ci_init_smc_table()
3647 table->MemoryThermThrottleEnable = 1; in ci_init_smc_table()
3648 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3649 table->PCIeGenInterval = 1; in ci_init_smc_table()
3651 table->SVI2Enable = 1; in ci_init_smc_table()
3653 table->SVI2Enable = 0; in ci_init_smc_table()
3655 table->ThermGpio = 17; in ci_init_smc_table()
3656 table->SclkStepSize = 0x4000; in ci_init_smc_table()
3658 table->SystemFlags = cpu_to_be32(table->SystemFlags); in ci_init_smc_table()
3659 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); in ci_init_smc_table()
3660 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); in ci_init_smc_table()
3661 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); in ci_init_smc_table()
3662 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); in ci_init_smc_table()
3663 table->SclkStepSize = cpu_to_be32(table->SclkStepSize); in ci_init_smc_table()
3664 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); in ci_init_smc_table()
3665 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); in ci_init_smc_table()
3666 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); in ci_init_smc_table()
3667 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); in ci_init_smc_table()
3668 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); in ci_init_smc_table()
3669 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); in ci_init_smc_table()
3670 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); in ci_init_smc_table()
3671 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); in ci_init_smc_table()
3676 (u8 *)&table->SystemFlags, in ci_init_smc_table()
4085 struct radeon_vce_clock_voltage_dependency_table *table = in ci_get_vce_boot_level() local
4088 for (i = 0; i < table->count; i++) { in ci_get_vce_boot_level()
4089 if (table->entries[i].evclk >= min_evclk) in ci_get_vce_boot_level()
4093 return table->count - 1; in ci_get_vce_boot_level()
4319 struct ci_mc_reg_table *table) in ci_set_mc_special_registers() argument
4325 for (i = 0, j = table->last; i < table->last; i++) { in ci_set_mc_special_registers()
4328 switch(table->mc_reg_address[i].s1 << 2) { in ci_set_mc_special_registers()
4331 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in ci_set_mc_special_registers()
4332 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in ci_set_mc_special_registers()
4333 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4334 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4335 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in ci_set_mc_special_registers()
4342 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in ci_set_mc_special_registers()
4343 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in ci_set_mc_special_registers()
4344 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4345 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4346 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
4348 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in ci_set_mc_special_registers()
4355 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers()
4356 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers()
4357 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4358 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4359 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in ci_set_mc_special_registers()
4368 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in ci_set_mc_special_registers()
4369 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in ci_set_mc_special_registers()
4370 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4371 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4372 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
4384 table->last = j; in ci_set_mc_special_registers()
4462 static void ci_set_valid_flag(struct ci_mc_reg_table *table) in ci_set_valid_flag() argument
4466 for (i = 0; i < table->last; i++) { in ci_set_valid_flag()
4467 for (j = 1; j < table->num_entries; j++) { in ci_set_valid_flag()
4468 if (table->mc_reg_table_entry[j-1].mc_data[i] != in ci_set_valid_flag()
4469 table->mc_reg_table_entry[j].mc_data[i]) { in ci_set_valid_flag()
4470 table->valid_flag |= 1 << i; in ci_set_valid_flag()
4477 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) in ci_set_s0_mc_reg_index() argument
4482 for (i = 0; i < table->last; i++) { in ci_set_s0_mc_reg_index()
4483 table->mc_reg_address[i].s0 = in ci_set_s0_mc_reg_index()
4484 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in ci_set_s0_mc_reg_index()
4485 address : table->mc_reg_address[i].s1; in ci_set_s0_mc_reg_index()
4489 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, in ci_copy_vbios_mc_reg_table() argument
4494 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) in ci_copy_vbios_mc_reg_table()
4496 if (table->num_entries > MAX_AC_TIMING_ENTRIES) in ci_copy_vbios_mc_reg_table()
4499 for (i = 0; i < table->last; i++) in ci_copy_vbios_mc_reg_table()
4500 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in ci_copy_vbios_mc_reg_table()
4502 ci_table->last = table->last; in ci_copy_vbios_mc_reg_table()
4504 for (i = 0; i < table->num_entries; i++) { in ci_copy_vbios_mc_reg_table()
4506 table->mc_reg_table_entry[i].mclk_max; in ci_copy_vbios_mc_reg_table()
4507 for (j = 0; j < table->last; j++) in ci_copy_vbios_mc_reg_table()
4509 table->mc_reg_table_entry[i].mc_data[j]; in ci_copy_vbios_mc_reg_table()
4511 ci_table->num_entries = table->num_entries; in ci_copy_vbios_mc_reg_table()
4517 struct ci_mc_reg_table *table) in ci_register_patching_mc_seq() argument
4529 for (i = 0; i < table->last; i++) { in ci_register_patching_mc_seq()
4530 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) in ci_register_patching_mc_seq()
4532 switch(table->mc_reg_address[i].s1 >> 2) { in ci_register_patching_mc_seq()
4534 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4535 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4536 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4537 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4538 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) | in ci_register_patching_mc_seq()
4543 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4544 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4545 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4546 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4547 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | in ci_register_patching_mc_seq()
4552 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4553 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4554 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4555 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4556 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | in ci_register_patching_mc_seq()
4561 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4562 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4563 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4564 table->mc_reg_table_entry[k].mc_data[i] = 0; in ci_register_patching_mc_seq()
4568 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4569 if (table->mc_reg_table_entry[k].mclk_max == 125000) in ci_register_patching_mc_seq()
4570 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4571 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | in ci_register_patching_mc_seq()
4573 else if (table->mc_reg_table_entry[k].mclk_max == 137500) in ci_register_patching_mc_seq()
4574 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4575 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | in ci_register_patching_mc_seq()
4580 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4581 if (table->mc_reg_table_entry[k].mclk_max == 125000) in ci_register_patching_mc_seq()
4582 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4583 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | in ci_register_patching_mc_seq()
4585 else if (table->mc_reg_table_entry[k].mclk_max == 137500) in ci_register_patching_mc_seq()
4586 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4587 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | in ci_register_patching_mc_seq()
4609 struct atom_mc_reg_table *table; in ci_initialize_mc_reg_table() local
4614 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); in ci_initialize_mc_reg_table()
4615 if (!table) in ci_initialize_mc_reg_table()
4639 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); in ci_initialize_mc_reg_table()
4643 ret = ci_copy_vbios_mc_reg_table(table, ci_table); in ci_initialize_mc_reg_table()
4660 kfree(table); in ci_initialize_mc_reg_table()
4969 struct radeon_clock_voltage_dependency_table *table) in ci_patch_clock_voltage_dependency_table_with_vddc_leakage() argument
4973 if (table) { in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4974 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4975 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4980 struct radeon_clock_voltage_dependency_table *table) in ci_patch_clock_voltage_dependency_table_with_vddci_leakage() argument
4984 if (table) { in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4985 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4986 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4991 struct radeon_vce_clock_voltage_dependency_table *table) in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage() argument
4995 if (table) { in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4996 for (i = 0; i < table->count; i++) in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4997 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
5002 struct radeon_uvd_clock_voltage_dependency_table *table) in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage() argument
5006 if (table) { in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
5007 for (i = 0; i < table->count; i++) in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
5008 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
5013 struct radeon_phase_shedding_limits_table *table) in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage() argument
5017 if (table) { in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5018 for (i = 0; i < table->count; i++) in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5019 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage); in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5024 struct radeon_clock_and_voltage_limits *table) in ci_patch_clock_voltage_limits_with_vddc_leakage() argument
5026 if (table) { in ci_patch_clock_voltage_limits_with_vddc_leakage()
5027 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5028 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5033 struct radeon_cac_leakage_table *table) in ci_patch_cac_leakage_table_with_vddc_leakage() argument
5037 if (table) { in ci_patch_cac_leakage_table_with_vddc_leakage()
5038 for (i = 0; i < table->count; i++) in ci_patch_cac_leakage_table_with_vddc_leakage()
5039 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc); in ci_patch_cac_leakage_table_with_vddc_leakage()