134 			      struct radeon_ib *ib)  in cik_sdma_ring_ib_execute()  argument
136 	struct radeon_ring *ring = &rdev->ring[ib->ring];  in cik_sdma_ring_ib_execute()
137 	u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf;  in cik_sdma_ring_ib_execute()
155 	radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */  in cik_sdma_ring_ib_execute()
156 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));  in cik_sdma_ring_ib_execute()
157 	radeon_ring_write(ring, ib->length_dw);  in cik_sdma_ring_ib_execute()
704 	struct radeon_ib ib;  in cik_sdma_ib_test()  local
721 	r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);  in cik_sdma_ib_test()
727 	ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);  in cik_sdma_ib_test()
728 	ib.ptr[1] = lower_32_bits(gpu_addr);  in cik_sdma_ib_test()
729 	ib.ptr[2] = upper_32_bits(gpu_addr);  in cik_sdma_ib_test()
730 	ib.ptr[3] = 1;  in cik_sdma_ib_test()
731 	ib.ptr[4] = 0xDEADBEEF;  in cik_sdma_ib_test()
732 	ib.length_dw = 5;  in cik_sdma_ib_test()
734 	r = radeon_ib_schedule(rdev, &ib, NULL, false);  in cik_sdma_ib_test()
736 		radeon_ib_free(rdev, &ib);  in cik_sdma_ib_test()
740 	r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(  in cik_sdma_ib_test()
757 		DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);  in cik_sdma_ib_test()
762 	radeon_ib_free(rdev, &ib);  in cik_sdma_ib_test()
804 			    struct radeon_ib *ib,  in cik_sdma_vm_copy_pages()  argument
813 		ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,  in cik_sdma_vm_copy_pages()
815 		ib->ptr[ib->length_dw++] = bytes;  in cik_sdma_vm_copy_pages()
816 		ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */  in cik_sdma_vm_copy_pages()
817 		ib->ptr[ib->length_dw++] = lower_32_bits(src);  in cik_sdma_vm_copy_pages()
818 		ib->ptr[ib->length_dw++] = upper_32_bits(src);  in cik_sdma_vm_copy_pages()
819 		ib->ptr[ib->length_dw++] = lower_32_bits(pe);  in cik_sdma_vm_copy_pages()
820 		ib->ptr[ib->length_dw++] = upper_32_bits(pe);  in cik_sdma_vm_copy_pages()
842 			     struct radeon_ib *ib,  in cik_sdma_vm_write_pages()  argument
856 		ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,  in cik_sdma_vm_write_pages()
858 		ib->ptr[ib->length_dw++] = pe;  in cik_sdma_vm_write_pages()
859 		ib->ptr[ib->length_dw++] = upper_32_bits(pe);  in cik_sdma_vm_write_pages()
860 		ib->ptr[ib->length_dw++] = ndw;  in cik_sdma_vm_write_pages()
871 			ib->ptr[ib->length_dw++] = value;  in cik_sdma_vm_write_pages()
872 			ib->ptr[ib->length_dw++] = upper_32_bits(value);  in cik_sdma_vm_write_pages()
891 			   struct radeon_ib *ib,  in cik_sdma_vm_set_pages()  argument
910 		ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);  in cik_sdma_vm_set_pages()
911 		ib->ptr[ib->length_dw++] = pe; /* dst addr */  in cik_sdma_vm_set_pages()
912 		ib->ptr[ib->length_dw++] = upper_32_bits(pe);  in cik_sdma_vm_set_pages()
913 		ib->ptr[ib->length_dw++] = flags; /* mask */  in cik_sdma_vm_set_pages()
914 		ib->ptr[ib->length_dw++] = 0;  in cik_sdma_vm_set_pages()
915 		ib->ptr[ib->length_dw++] = value; /* value */  in cik_sdma_vm_set_pages()
916 		ib->ptr[ib->length_dw++] = upper_32_bits(value);  in cik_sdma_vm_set_pages()
917 		ib->ptr[ib->length_dw++] = incr; /* increment size */  in cik_sdma_vm_set_pages()
918 		ib->ptr[ib->length_dw++] = 0;  in cik_sdma_vm_set_pages()
919 		ib->ptr[ib->length_dw++] = ndw; /* number of entries */  in cik_sdma_vm_set_pages()
933 void cik_sdma_vm_pad_ib(struct radeon_ib *ib)  in cik_sdma_vm_pad_ib()  argument
935 	while (ib->length_dw & 0x7)  in cik_sdma_vm_pad_ib()
936 		ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);  in cik_sdma_vm_pad_ib()