3029 	radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));  in evergreen_ring_ib_execute()
3030 	radeon_ring_write(ring, 1);  in evergreen_ring_ib_execute()
3034 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in evergreen_ring_ib_execute()
3035 		radeon_ring_write(ring, ((ring->rptr_save_reg -   in evergreen_ring_ib_execute()
3037 		radeon_ring_write(ring, next_rptr);  in evergreen_ring_ib_execute()
3040 		radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));  in evergreen_ring_ib_execute()
3041 		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);  in evergreen_ring_ib_execute()
3042 		radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));  in evergreen_ring_ib_execute()
3043 		radeon_ring_write(ring, next_rptr);  in evergreen_ring_ib_execute()
3044 		radeon_ring_write(ring, 0);  in evergreen_ring_ib_execute()
3047 	radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));  in evergreen_ring_ib_execute()
3048 	radeon_ring_write(ring,  in evergreen_ring_ib_execute()
3053 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);  in evergreen_ring_ib_execute()
3054 	radeon_ring_write(ring, ib->length_dw);  in evergreen_ring_ib_execute()
3101 	radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));  in evergreen_cp_start()
3102 	radeon_ring_write(ring, 0x1);  in evergreen_cp_start()
3103 	radeon_ring_write(ring, 0x0);  in evergreen_cp_start()
3104 	radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);  in evergreen_cp_start()
3105 	radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));  in evergreen_cp_start()
3106 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3107 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3120 	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in evergreen_cp_start()
3121 	radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);  in evergreen_cp_start()
3124 		radeon_ring_write(ring, evergreen_default_state[i]);  in evergreen_cp_start()
3126 	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in evergreen_cp_start()
3127 	radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);  in evergreen_cp_start()
3130 	radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in evergreen_cp_start()
3131 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3134 	radeon_ring_write(ring, 0xc0026f00);  in evergreen_cp_start()
3135 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3136 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3137 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3140 	radeon_ring_write(ring, 0xc0036f00);  in evergreen_cp_start()
3141 	radeon_ring_write(ring, 0x00000bc4);  in evergreen_cp_start()
3142 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3143 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3144 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3146 	radeon_ring_write(ring, 0xc0026900);  in evergreen_cp_start()
3147 	radeon_ring_write(ring, 0x00000316);  in evergreen_cp_start()
3148 	radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */  in evergreen_cp_start()
3149 	radeon_ring_write(ring, 0x00000010); /*  */  in evergreen_cp_start()