44 	struct radeon_ring *ring = &rdev->ring[fence->ring];  in evergreen_dma_fence_ring_emit()  local
45 	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;  in evergreen_dma_fence_ring_emit()
47 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));  in evergreen_dma_fence_ring_emit()
48 	radeon_ring_write(ring, addr & 0xfffffffc);  in evergreen_dma_fence_ring_emit()
49 	radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));  in evergreen_dma_fence_ring_emit()
50 	radeon_ring_write(ring, fence->seq);  in evergreen_dma_fence_ring_emit()
52 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));  in evergreen_dma_fence_ring_emit()
54 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));  in evergreen_dma_fence_ring_emit()
55 	radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));  in evergreen_dma_fence_ring_emit()
56 	radeon_ring_write(ring, 1);  in evergreen_dma_fence_ring_emit()
70 	struct radeon_ring *ring = &rdev->ring[ib->ring];  in evergreen_dma_ring_ib_execute()  local
73 		u32 next_rptr = ring->wptr + 4;  in evergreen_dma_ring_ib_execute()
77 		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));  in evergreen_dma_ring_ib_execute()
78 		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);  in evergreen_dma_ring_ib_execute()
79 		radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);  in evergreen_dma_ring_ib_execute()
80 		radeon_ring_write(ring, next_rptr);  in evergreen_dma_ring_ib_execute()
86 	while ((ring->wptr & 7) != 5)  in evergreen_dma_ring_ib_execute()
87 		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));  in evergreen_dma_ring_ib_execute()
88 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));  in evergreen_dma_ring_ib_execute()
89 	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));  in evergreen_dma_ring_ib_execute()
90 	radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));  in evergreen_dma_ring_ib_execute()
116 	struct radeon_ring *ring = &rdev->ring[ring_index];  in evergreen_copy_dma()  local
125 	r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);  in evergreen_copy_dma()
133 	radeon_sync_rings(rdev, &sync, ring->idx);  in evergreen_copy_dma()
140 		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));  in evergreen_copy_dma()
141 		radeon_ring_write(ring, dst_offset & 0xfffffffc);  in evergreen_copy_dma()
142 		radeon_ring_write(ring, src_offset & 0xfffffffc);  in evergreen_copy_dma()
143 		radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);  in evergreen_copy_dma()
144 		radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);  in evergreen_copy_dma()
149 	r = radeon_fence_emit(rdev, &fence, ring->idx);  in evergreen_copy_dma()
151 		radeon_ring_unlock_undo(rdev, ring);  in evergreen_copy_dma()
156 	radeon_ring_unlock_commit(rdev, ring, false);  in evergreen_copy_dma()
171 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)  in evergreen_dma_is_lockup()  argument
176 		radeon_ring_lockup_update(rdev, ring);  in evergreen_dma_is_lockup()
179 	return radeon_ring_test_lockup(rdev, ring);  in evergreen_dma_is_lockup()