Lines Matching refs:sclk
810 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()
811 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()
829 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
830 &ps->performance_levels[0].sclk, in ni_apply_state_adjust_rules()
834 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in ni_apply_state_adjust_rules()
835 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in ni_apply_state_adjust_rules()
864 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
865 &ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
874 ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
1621 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk); in ni_populate_memory_timing_parameters()
1624 radeon_atom_set_engine_dram_timings(rdev, pl->sclk, pl->mclk); in ni_populate_memory_timing_parameters()
1709 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = in ni_populate_smc_initial_state()
1711 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = in ni_populate_smc_initial_state()
1713 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = in ni_populate_smc_initial_state()
1715 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = in ni_populate_smc_initial_state()
1717 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = in ni_populate_smc_initial_state()
1719 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = in ni_populate_smc_initial_state()
1721 table->initialState.levels[0].sclk.sclk_value = in ni_populate_smc_initial_state()
1722 cpu_to_be32(initial_state->performance_levels[0].sclk); in ni_populate_smc_initial_state()
1912 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in ni_populate_smc_acpi_state()
1913 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in ni_populate_smc_acpi_state()
1914 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in ni_populate_smc_acpi_state()
1915 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4); in ni_populate_smc_acpi_state()
1917 table->ACPIState.levels[0].sclk.sclk_value = 0; in ni_populate_smc_acpi_state()
1998 NISLANDS_SMC_SCLK_VALUE *sclk) in ni_calculate_sclk_params() argument
2056 sclk->sclk_value = engine_clock; in ni_calculate_sclk_params()
2057 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; in ni_calculate_sclk_params()
2058 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; in ni_calculate_sclk_params()
2059 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; in ni_calculate_sclk_params()
2060 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; in ni_calculate_sclk_params()
2061 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; in ni_calculate_sclk_params()
2062 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; in ni_calculate_sclk_params()
2069 NISLANDS_SMC_SCLK_VALUE *sclk) in ni_populate_sclk_value() argument
2076 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); in ni_populate_sclk_value()
2077 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); in ni_populate_sclk_value()
2078 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); in ni_populate_sclk_value()
2079 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); in ni_populate_sclk_value()
2080 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); in ni_populate_sclk_value()
2081 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); in ni_populate_sclk_value()
2082 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); in ni_populate_sclk_value()
2098 u32 sclk = 0; in ni_init_smc_spll_table() local
2110 ret = ni_calculate_sclk_params(rdev, sclk, &sclk_params); in ni_init_smc_spll_table()
2146 sclk += 512; in ni_init_smc_spll_table()
2322 ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk); in ni_convert_power_level_to_smc()
2354 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, in ni_convert_power_level_to_smc()
2359 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1); in ni_convert_power_level_to_smc()
2416 state->performance_levels[i + 1].sclk, in ni_populate_smc_t()
2417 state->performance_levels[i].sclk, in ni_populate_smc_t()
2424 state->performance_levels[i + 1].sclk, in ni_populate_smc_t()
2425 state->performance_levels[i].sclk, in ni_populate_smc_t()
2500 prev_sclk = state->performance_levels[i-1].sclk; in ni_populate_power_containment_values()
2501 max_sclk = state->performance_levels[i].sclk; in ni_populate_power_containment_values()
2515 if (min_sclk < state->performance_levels[0].sclk) in ni_populate_power_containment_values()
2516 min_sclk = state->performance_levels[0].sclk; in ni_populate_power_containment_values()
2573 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in ni_populate_sq_ramping_values()
2630 u32 threshold = state->performance_levels[state->performance_level_count - 1].sclk * 100 / 100; in ni_convert_power_state_to_smc()
2651 (state->performance_levels[i].sclk < threshold) ? in ni_convert_power_state_to_smc()
3517 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock()
3518 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_before_set_eng_clock()
3535 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < in ni_set_uvd_clock_after_set_eng_clock()
3536 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_after_set_eng_clock()
3929 pl->sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); in ni_parse_pplib_clock_info()
3930 pl->sclk |= clock_info->evergreen.ucEngineClockHigh << 16; in ni_parse_pplib_clock_info()
3969 pl->sclk = rdev->clock.default_sclk; in ni_parse_pplib_clock_info()
3976 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in ni_parse_pplib_clock_info()
4256 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in ni_dpm_init()
4291 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in ni_dpm_print_power_state()
4294 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci); in ni_dpm_print_power_state()
4316 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci); in ni_dpm_debugfs_print_current_performance_level()
4334 return pl->sclk; in ni_dpm_get_current_sclk()
4362 return requested_state->performance_levels[0].sclk; in ni_dpm_get_sclk()
4364 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; in ni_dpm_get_sclk()