Lines Matching refs:args
218 struct drm_radeon_gem_info *args = data; in radeon_gem_info_ioctl() local
223 args->vram_size = (u64)man->size << PAGE_SHIFT; in radeon_gem_info_ioctl()
224 args->vram_visible = rdev->mc.visible_vram_size; in radeon_gem_info_ioctl()
225 args->vram_visible -= rdev->vram_pin_size; in radeon_gem_info_ioctl()
226 args->gart_size = rdev->mc.gtt_size; in radeon_gem_info_ioctl()
227 args->gart_size -= rdev->gart_pin_size; in radeon_gem_info_ioctl()
252 struct drm_radeon_gem_create *args = data; in radeon_gem_create_ioctl() local
259 args->size = roundup(args->size, PAGE_SIZE); in radeon_gem_create_ioctl()
260 r = radeon_gem_object_create(rdev, args->size, args->alignment, in radeon_gem_create_ioctl()
261 args->initial_domain, args->flags, in radeon_gem_create_ioctl()
276 args->handle = handle; in radeon_gem_create_ioctl()
285 struct drm_radeon_gem_userptr *args = data; in radeon_gem_userptr_ioctl() local
291 if (offset_in_page(args->addr | args->size)) in radeon_gem_userptr_ioctl()
295 if (args->flags & ~(RADEON_GEM_USERPTR_READONLY | in radeon_gem_userptr_ioctl()
300 if (args->flags & RADEON_GEM_USERPTR_READONLY) { in radeon_gem_userptr_ioctl()
305 } else if (!(args->flags & RADEON_GEM_USERPTR_ANONONLY) || in radeon_gem_userptr_ioctl()
306 !(args->flags & RADEON_GEM_USERPTR_REGISTER)) { in radeon_gem_userptr_ioctl()
316 r = radeon_gem_object_create(rdev, args->size, 0, in radeon_gem_userptr_ioctl()
323 r = radeon_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); in radeon_gem_userptr_ioctl()
327 if (args->flags & RADEON_GEM_USERPTR_REGISTER) { in radeon_gem_userptr_ioctl()
328 r = radeon_mn_register(bo, args->addr); in radeon_gem_userptr_ioctl()
333 if (args->flags & RADEON_GEM_USERPTR_VALIDATE) { in radeon_gem_userptr_ioctl()
355 args->handle = handle; in radeon_gem_userptr_ioctl()
375 struct drm_radeon_gem_set_domain *args = data; in radeon_gem_set_domain_ioctl() local
385 gobj = drm_gem_object_lookup(filp, args->handle); in radeon_gem_set_domain_ioctl()
392 r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain); in radeon_gem_set_domain_ioctl()
424 struct drm_radeon_gem_mmap *args = data; in radeon_gem_mmap_ioctl() local
426 return radeon_mode_dumb_mmap(filp, dev, args->handle, &args->addr_ptr); in radeon_gem_mmap_ioctl()
432 struct drm_radeon_gem_busy *args = data; in radeon_gem_busy_ioctl() local
438 gobj = drm_gem_object_lookup(filp, args->handle); in radeon_gem_busy_ioctl()
451 args->domain = radeon_mem_type_to_domain(cur_placement); in radeon_gem_busy_ioctl()
460 struct drm_radeon_gem_wait_idle *args = data; in radeon_gem_wait_idle_ioctl() local
467 gobj = drm_gem_object_lookup(filp, args->handle); in radeon_gem_wait_idle_ioctl()
492 struct drm_radeon_gem_set_tiling *args = data; in radeon_gem_set_tiling_ioctl() local
497 DRM_DEBUG("%d \n", args->handle); in radeon_gem_set_tiling_ioctl()
498 gobj = drm_gem_object_lookup(filp, args->handle); in radeon_gem_set_tiling_ioctl()
502 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl()
510 struct drm_radeon_gem_get_tiling *args = data; in radeon_gem_get_tiling_ioctl() local
516 gobj = drm_gem_object_lookup(filp, args->handle); in radeon_gem_get_tiling_ioctl()
523 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
595 struct drm_radeon_gem_va *args = data; in radeon_gem_va_ioctl() local
605 args->operation = RADEON_VA_RESULT_ERROR; in radeon_gem_va_ioctl()
614 if (args->vm_id) { in radeon_gem_va_ioctl()
615 args->operation = RADEON_VA_RESULT_ERROR; in radeon_gem_va_ioctl()
619 if (args->offset < RADEON_VA_RESERVED_SIZE) { in radeon_gem_va_ioctl()
622 (unsigned long)args->offset, in radeon_gem_va_ioctl()
624 args->operation = RADEON_VA_RESULT_ERROR; in radeon_gem_va_ioctl()
633 if ((args->flags & invalid_flags)) { in radeon_gem_va_ioctl()
635 args->flags, invalid_flags); in radeon_gem_va_ioctl()
636 args->operation = RADEON_VA_RESULT_ERROR; in radeon_gem_va_ioctl()
640 switch (args->operation) { in radeon_gem_va_ioctl()
646 args->operation); in radeon_gem_va_ioctl()
647 args->operation = RADEON_VA_RESULT_ERROR; in radeon_gem_va_ioctl()
651 gobj = drm_gem_object_lookup(filp, args->handle); in radeon_gem_va_ioctl()
653 args->operation = RADEON_VA_RESULT_ERROR; in radeon_gem_va_ioctl()
659 args->operation = RADEON_VA_RESULT_ERROR; in radeon_gem_va_ioctl()
665 args->operation = RADEON_VA_RESULT_ERROR; in radeon_gem_va_ioctl()
671 switch (args->operation) { in radeon_gem_va_ioctl()
674 args->operation = RADEON_VA_RESULT_VA_EXIST; in radeon_gem_va_ioctl()
675 args->offset = bo_va->it.start * RADEON_GPU_PAGE_SIZE; in radeon_gem_va_ioctl()
679 r = radeon_vm_bo_set_addr(rdev, bo_va, args->offset, args->flags); in radeon_gem_va_ioctl()
689 args->operation = RADEON_VA_RESULT_OK; in radeon_gem_va_ioctl()
691 args->operation = RADEON_VA_RESULT_ERROR; in radeon_gem_va_ioctl()
701 struct drm_radeon_gem_op *args = data; in radeon_gem_op_ioctl() local
706 gobj = drm_gem_object_lookup(filp, args->handle); in radeon_gem_op_ioctl()
720 switch (args->op) { in radeon_gem_op_ioctl()
722 args->value = robj->initial_domain; in radeon_gem_op_ioctl()
725 robj->initial_domain = args->value & (RADEON_GEM_DOMAIN_VRAM | in radeon_gem_op_ioctl()
741 struct drm_mode_create_dumb *args) in radeon_mode_dumb_create() argument
748 args->pitch = radeon_align_pitch(rdev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8); in radeon_mode_dumb_create()
749 args->size = args->pitch * args->height; in radeon_mode_dumb_create()
750 args->size = ALIGN(args->size, PAGE_SIZE); in radeon_mode_dumb_create()
752 r = radeon_gem_object_create(rdev, args->size, 0, in radeon_mode_dumb_create()
764 args->handle = handle; in radeon_mode_dumb_create()