Lines Matching refs:radeon_ring_write
70 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start()
71 radeon_ring_write(ring, in rv515_ring_start()
76 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
77 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); in rv515_ring_start()
78 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start()
79 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); in rv515_ring_start()
80 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start()
81 radeon_ring_write(ring, 0); in rv515_ring_start()
82 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start()
83 radeon_ring_write(ring, 0); in rv515_ring_start()
84 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); in rv515_ring_start()
85 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); in rv515_ring_start()
86 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); in rv515_ring_start()
87 radeon_ring_write(ring, 0); in rv515_ring_start()
88 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); in rv515_ring_start()
89 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); in rv515_ring_start()
90 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); in rv515_ring_start()
91 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); in rv515_ring_start()
92 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
93 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); in rv515_ring_start()
94 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); in rv515_ring_start()
95 radeon_ring_write(ring, 0); in rv515_ring_start()
96 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); in rv515_ring_start()
97 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); in rv515_ring_start()
98 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); in rv515_ring_start()
99 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); in rv515_ring_start()
100 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); in rv515_ring_start()
101 radeon_ring_write(ring, in rv515_ring_start()
110 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); in rv515_ring_start()
111 radeon_ring_write(ring, in rv515_ring_start()
119 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); in rv515_ring_start()
120 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); in rv515_ring_start()
121 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); in rv515_ring_start()
122 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); in rv515_ring_start()
123 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); in rv515_ring_start()
124 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); in rv515_ring_start()
125 radeon_ring_write(ring, PACKET0(0x20C8, 0)); in rv515_ring_start()
126 radeon_ring_write(ring, 0); in rv515_ring_start()