191 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));  in si_dma_vm_flush()
193 		radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2));  in si_dma_vm_flush()
195 …radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> …  in si_dma_vm_flush()
197 	radeon_ring_write(ring, pd_addr >> 12);  in si_dma_vm_flush()
200 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));  in si_dma_vm_flush()
201 	radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));  in si_dma_vm_flush()
202 	radeon_ring_write(ring, 1);  in si_dma_vm_flush()
205 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));  in si_dma_vm_flush()
206 	radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));  in si_dma_vm_flush()
207 	radeon_ring_write(ring, 1 << vm_id);  in si_dma_vm_flush()
210 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0));  in si_dma_vm_flush()
211 	radeon_ring_write(ring, VM_INVALIDATE_REQUEST);  in si_dma_vm_flush()
212 	radeon_ring_write(ring, 0xff << 16); /* retry */  in si_dma_vm_flush()
213 	radeon_ring_write(ring, 1 << vm_id); /* mask */  in si_dma_vm_flush()
214 	radeon_ring_write(ring, 0); /* value */  in si_dma_vm_flush()
215 	radeon_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */  in si_dma_vm_flush()
263 		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));  in si_copy_dma()
264 		radeon_ring_write(ring, lower_32_bits(dst_offset));  in si_copy_dma()
265 		radeon_ring_write(ring, lower_32_bits(src_offset));  in si_copy_dma()
266 		radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);  in si_copy_dma()
267 		radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);  in si_copy_dma()