141 	dd->pcidev = pdev;  in qib_pcie_ddinit()
184 	pci_disable_device(dd->pcidev);  in qib_pcie_ddcleanup()
185 	pci_release_regions(dd->pcidev);  in qib_pcie_ddcleanup()
187 	pci_set_drvdata(dd->pcidev, NULL);  in qib_pcie_ddcleanup()
198 	ret = pci_msix_vec_count(dd->pcidev);  in qib_msix_setup()
214 	ret = pci_enable_msix_range(dd->pcidev, msix_entry, 1, nvec);  in qib_msix_setup()
236 	qib_enable_intx(dd->pcidev);  in qib_msix_setup()
246 	struct pci_dev *pdev = dd->pcidev;  in qib_msi_setup()
275 	if (!pci_is_pcie(dd->pcidev)) {  in qib_pcie_params()
283 	pos = dd->pcidev->msix_cap;  in qib_pcie_params()
288 		pos = dd->pcidev->msi_cap;  in qib_pcie_params()
295 		qib_enable_intx(dd->pcidev);  in qib_pcie_params()
297 	pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);  in qib_pcie_params()
357 	pos = dd->pcidev->msi_cap;  in qib_reinit_intr()
365 	pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,  in qib_reinit_intr()
367 	pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,  in qib_reinit_intr()
369 	pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);  in qib_reinit_intr()
372 		pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,  in qib_reinit_intr()
376 	pci_write_config_word(dd->pcidev, pos +  in qib_reinit_intr()
382 		qib_enable_intx(dd->pcidev);  in qib_reinit_intr()
387 	pci_set_master(dd->pcidev);  in qib_reinit_intr()
400 	pci_disable_msi(dd->pcidev);  in qib_nomsi()
408 	pci_disable_msix(dd->pcidev);  in qib_nomsix()
450 	pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd);  in qib_pcie_getcmd()
451 	pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);  in qib_pcie_getcmd()
452 	pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);  in qib_pcie_getcmd()
459 	r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,  in qib_pcie_reenable()
463 	r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,  in qib_pcie_reenable()
468 	pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd);  in qib_pcie_reenable()
469 	pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);  in qib_pcie_reenable()
470 	pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);  in qib_pcie_reenable()
471 	r = pci_enable_device(dd->pcidev);  in qib_pcie_reenable()
499 	parent = dd->pcidev->bus->self;  in qib_tune_pcie_coalesce()
501 		qib_devinfo(dd->pcidev, "Parent not root\n");  in qib_tune_pcie_coalesce()
563 	parent = dd->pcidev->bus->self;  in qib_tune_pcie_caps()
565 		qib_devinfo(dd->pcidev, "Parent not root\n");  in qib_tune_pcie_caps()
569 	if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))  in qib_tune_pcie_caps()
575 	ep_mpss = dd->pcidev->pcie_mpss;  in qib_tune_pcie_caps()
576 	ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;  in qib_tune_pcie_caps()
593 		pcie_set_mps(dd->pcidev, 128 << ep_mps);  in qib_tune_pcie_caps()
607 	ep_mrrs = pcie_get_readrq(dd->pcidev);  in qib_tune_pcie_caps()
615 		pcie_set_readrq(dd->pcidev, ep_mrrs);  in qib_tune_pcie_caps()