165 	DBG(0x1000, " port %#x, value %#x",  in fcpci_read_isac()
178 	DBG(0x1000, " port %#x, value %#x",  in fcpci_write_isac()
228 	DBG(0x40, "hdlc %c wr%x ctrl %x",  in __fcpci_write_ctrl()
258 	DBG(0x1000, " port %#x, value %#x",  in fcpci2_read_isac()
270 	DBG(0x1000, " port %#x, value %#x",  in fcpci2_write_isac()
318 	DBG(0x40, "hdlc %c wr%x ctrl %x",  in fcpci2_write_ctrl()
347 	DBG(0x40, "hdlc %c wr%x ctrl %x",  in __fcpnp_write_ctrl()
378 	DBG(2, "pr %#x", pr);  in B_L1L2()
390 	DBG(0x40, "hdlc_fill_fifo");  in hdlc_fill_fifo()
402 	DBG(0x40, "hdlc_fill_fifo %d/%d", count, bcs->tx_skb->len);  in hdlc_fill_fifo()
439 	DBG(0x10, "hdlc_empty_fifo %d", count);  in hdlc_empty_fifo()
441 		DBG(0x10, "hdlc_empty_fifo: incoming packet too large");  in hdlc_empty_fifo()
475 		DBG(0x10, "RDO");  in hdlc_rpr_irq()
505 			DBG(0x10, "ch%d invalid frame %#x",  in hdlc_rpr_irq()
526 		DBG(0x10, "XDU without skb");  in hdlc_xdu_irq()
557 	DBG(0x10, "ch%d stat %#x", bcs->channel, stat);  in hdlc_irq_one()
559 		DBG(0x10, "RPR");  in hdlc_irq_one()
563 		DBG(0x10, "XDU");  in hdlc_irq_one()
569 		DBG(0x10, "XPR");  in hdlc_irq_one()
581 		DBG(0x10, "HDLC %c stat %#x", 'A' + nr, stat);  in hdlc_irq()
591 	DBG(0x40, "hdlc %c mode %d --> %d",  in modehdlc()
630 	DBG(0x10, "pr %#x", pr);  in fritz_b_l2l1()
641 		DBG(4, "B%d,PH_ACTIVATE_REQUEST %d", bcs->channel + 1, mode);  in fritz_b_l2l1()
646 		DBG(4, "B%d,PH_DEACTIVATE_REQUEST", bcs->channel + 1);  in fritz_b_l2l1()
665 	DBG(2, "STATUS0 %#x", val);  in fcpci2_irq()
685 	DBG(2, "sval %#x", sval);  in fcpci_irq()
720 	DBG(1, "");  in fcpcipnp_setup()
739 	DBG(1, "stat %#x Class %X Rev %d",  in fcpcipnp_setup()
811 	DBG(0x20, "HDLC A STA %x", val);  in fcpcipnp_setup()
813 	DBG(0x20, "HDLC B STA %x", val);  in fcpcipnp_setup()
830 	DBG(1, "");  in fcpcipnp_release()