Lines Matching refs:state
50 static u16 dib3000mc_read_word(struct dib3000mc_state *state, u16 reg) in dib3000mc_read_word() argument
55 { .addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2 }, in dib3000mc_read_word()
56 { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2 }, in dib3000mc_read_word()
59 if (i2c_transfer(state->i2c_adap, msg, 2) != 2) in dib3000mc_read_word()
65 static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val) in dib3000mc_write_word() argument
72 .addr = state->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4 in dib3000mc_write_word()
74 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; in dib3000mc_write_word()
77 static int dib3000mc_identify(struct dib3000mc_state *state) in dib3000mc_identify() argument
80 if ((value = dib3000mc_read_word(state, 1025)) != 0x01b3) { in dib3000mc_identify()
85 value = dib3000mc_read_word(state, 1026); in dib3000mc_identify()
90 state->dev_id = value; in dib3000mc_identify()
92 dprintk("-I- found DiB3000MC/P: %x\n",state->dev_id); in dib3000mc_identify()
97 static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u32 bw, u8 update_offset) in dib3000mc_set_timing() argument
101 if (state->timf == 0) { in dib3000mc_set_timing()
106 timf = state->timf; in dib3000mc_set_timing()
111 s16 tim_offs = dib3000mc_read_word(state, 416); in dib3000mc_set_timing()
120 state->timf = timf / (bw / 1000); in dib3000mc_set_timing()
125 dib3000mc_write_word(state, 23, (u16) (timf >> 16)); in dib3000mc_set_timing()
126 dib3000mc_write_word(state, 24, (u16) (timf ) & 0xffff); in dib3000mc_set_timing()
131 static int dib3000mc_setup_pwm_state(struct dib3000mc_state *state) in dib3000mc_setup_pwm_state() argument
133 u16 reg_51, reg_52 = state->cfg->agc->setup & 0xfefb; in dib3000mc_setup_pwm_state()
134 if (state->cfg->pwm3_inversion) { in dib3000mc_setup_pwm_state()
141 dib3000mc_write_word(state, 51, reg_51); in dib3000mc_setup_pwm_state()
142 dib3000mc_write_word(state, 52, reg_52); in dib3000mc_setup_pwm_state()
144 if (state->cfg->use_pwm3) in dib3000mc_setup_pwm_state()
145 dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0)); in dib3000mc_setup_pwm_state()
147 dib3000mc_write_word(state, 245, 0); in dib3000mc_setup_pwm_state()
149 dib3000mc_write_word(state, 1040, 0x3); in dib3000mc_setup_pwm_state()
153 static int dib3000mc_set_output_mode(struct dib3000mc_state *state, int mode) in dib3000mc_set_output_mode() argument
160 u16 smo_reg = dib3000mc_read_word(state, 206) & 0x0010; /* keep the pid_parse bit */ in dib3000mc_set_output_mode()
163 &state->demod, mode); in dib3000mc_set_output_mode()
197 dprintk("Unhandled output_mode passed to be set for demod %p\n",&state->demod); in dib3000mc_set_output_mode()
202 if ((state->cfg->output_mpeg2_in_188_bytes)) in dib3000mc_set_output_mode()
205 outreg = dib3000mc_read_word(state, 244) & 0x07FF; in dib3000mc_set_output_mode()
207 ret |= dib3000mc_write_word(state, 244, outreg); in dib3000mc_set_output_mode()
208 ret |= dib3000mc_write_word(state, 206, smo_reg); /*smo_ mode*/ in dib3000mc_set_output_mode()
209 ret |= dib3000mc_write_word(state, 207, fifo_threshold); /* synchronous fread */ in dib3000mc_set_output_mode()
210 ret |= dib3000mc_write_word(state, 1040, elecout); /* P_out_cfg */ in dib3000mc_set_output_mode()
214 static int dib3000mc_set_bandwidth(struct dib3000mc_state *state, u32 bw) in dib3000mc_set_bandwidth() argument
246 dib3000mc_write_word(state, reg, bw_cfg[reg - 6]); in dib3000mc_set_bandwidth()
247 dib3000mc_write_word(state, 12, 0x0000); in dib3000mc_set_bandwidth()
248 dib3000mc_write_word(state, 13, 0x03e8); in dib3000mc_set_bandwidth()
249 dib3000mc_write_word(state, 14, 0x0000); in dib3000mc_set_bandwidth()
250 dib3000mc_write_word(state, 15, 0x03f2); in dib3000mc_set_bandwidth()
251 dib3000mc_write_word(state, 16, 0x0001); in dib3000mc_set_bandwidth()
252 dib3000mc_write_word(state, 17, 0xb0d0); in dib3000mc_set_bandwidth()
254 dib3000mc_write_word(state, 18, 0x0393); in dib3000mc_set_bandwidth()
255 dib3000mc_write_word(state, 19, 0x8700); in dib3000mc_set_bandwidth()
258 dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]); in dib3000mc_set_bandwidth()
261 dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0); in dib3000mc_set_bandwidth()
274 static void dib3000mc_set_impulse_noise(struct dib3000mc_state *state, u8 mode, s16 nfft) in dib3000mc_set_impulse_noise() argument
278 dib3000mc_write_word(state, i, impulse_noise_val[i-58]); in dib3000mc_set_impulse_noise()
281 dib3000mc_write_word(state, 58, 0x3b); in dib3000mc_set_impulse_noise()
282 dib3000mc_write_word(state, 84, 0x00); in dib3000mc_set_impulse_noise()
283 dib3000mc_write_word(state, 85, 0x8200); in dib3000mc_set_impulse_noise()
286 dib3000mc_write_word(state, 34, 0x1294); in dib3000mc_set_impulse_noise()
287 dib3000mc_write_word(state, 35, 0x1ff8); in dib3000mc_set_impulse_noise()
289 dib3000mc_write_word(state, 55, dib3000mc_read_word(state, 55) | (1 << 10)); in dib3000mc_set_impulse_noise()
294 struct dib3000mc_state *state = demod->demodulator_priv; in dib3000mc_init() local
295 struct dibx000_agc_config *agc = state->cfg->agc; in dib3000mc_init()
298 dib3000mc_write_word(state, 1027, 0x8000); in dib3000mc_init()
299 dib3000mc_write_word(state, 1027, 0x0000); in dib3000mc_init()
302 dib3000mc_write_word(state, 140, 0x0000); in dib3000mc_init()
303 dib3000mc_write_word(state, 1031, 0); in dib3000mc_init()
305 if (state->cfg->mobile_mode) { in dib3000mc_init()
306 dib3000mc_write_word(state, 139, 0x0000); in dib3000mc_init()
307 dib3000mc_write_word(state, 141, 0x0000); in dib3000mc_init()
308 dib3000mc_write_word(state, 175, 0x0002); in dib3000mc_init()
309 dib3000mc_write_word(state, 1032, 0x0000); in dib3000mc_init()
311 dib3000mc_write_word(state, 139, 0x0001); in dib3000mc_init()
312 dib3000mc_write_word(state, 141, 0x0000); in dib3000mc_init()
313 dib3000mc_write_word(state, 175, 0x0000); in dib3000mc_init()
314 dib3000mc_write_word(state, 1032, 0x012C); in dib3000mc_init()
316 dib3000mc_write_word(state, 1033, 0x0000); in dib3000mc_init()
319 dib3000mc_write_word(state, 1037, 0x3130); in dib3000mc_init()
324 dib3000mc_write_word(state, 33, (5 << 0)); in dib3000mc_init()
325 dib3000mc_write_word(state, 88, (1 << 10) | (0x10 << 0)); in dib3000mc_init()
329 dib3000mc_write_word(state, 99, (1 << 9) | (0x20 << 0)); in dib3000mc_init()
331 if (state->cfg->phase_noise_mode == 0) in dib3000mc_init()
332 dib3000mc_write_word(state, 111, 0x00); in dib3000mc_init()
334 dib3000mc_write_word(state, 111, 0x02); in dib3000mc_init()
337 dib3000mc_write_word(state, 50, 0x8000); in dib3000mc_init()
340 dib3000mc_setup_pwm_state(state); in dib3000mc_init()
343 dib3000mc_write_word(state, 53, 0x87); in dib3000mc_init()
345 dib3000mc_write_word(state, 54, 0x87); in dib3000mc_init()
348 dib3000mc_write_word(state, 36, state->cfg->max_time); in dib3000mc_init()
349 …dib3000mc_write_word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12… in dib3000mc_init()
350 dib3000mc_write_word(state, 38, state->cfg->pwm3_value); in dib3000mc_init()
351 dib3000mc_write_word(state, 39, state->cfg->ln_adc_level); in dib3000mc_init()
354 dib3000mc_write_word(state, 40, 0x0179); in dib3000mc_init()
355 dib3000mc_write_word(state, 41, 0x03f0); in dib3000mc_init()
357 dib3000mc_write_word(state, 42, agc->agc1_max); in dib3000mc_init()
358 dib3000mc_write_word(state, 43, agc->agc1_min); in dib3000mc_init()
359 dib3000mc_write_word(state, 44, agc->agc2_max); in dib3000mc_init()
360 dib3000mc_write_word(state, 45, agc->agc2_min); in dib3000mc_init()
361 dib3000mc_write_word(state, 46, (agc->agc1_pt1 << 8) | agc->agc1_pt2); in dib3000mc_init()
362 dib3000mc_write_word(state, 47, (agc->agc1_slope1 << 8) | agc->agc1_slope2); in dib3000mc_init()
363 dib3000mc_write_word(state, 48, (agc->agc2_pt1 << 8) | agc->agc2_pt2); in dib3000mc_init()
364 dib3000mc_write_word(state, 49, (agc->agc2_slope1 << 8) | agc->agc2_slope2); in dib3000mc_init()
368 dib3000mc_write_word(state, 110, 3277); in dib3000mc_init()
370 dib3000mc_write_word(state, 26, 0x6680); in dib3000mc_init()
372 dib3000mc_write_word(state, 1, 4); in dib3000mc_init()
374 dib3000mc_write_word(state, 2, 4); in dib3000mc_init()
376 dib3000mc_write_word(state, 3, 0x1000); in dib3000mc_init()
378 dib3000mc_write_word(state, 5, 1); in dib3000mc_init()
380 dib3000mc_set_bandwidth(state, 8000); in dib3000mc_init()
383 dib3000mc_write_word(state, 4, 0x814); in dib3000mc_init()
385 dib3000mc_write_word(state, 21, (1 << 9) | 0x164); in dib3000mc_init()
386 dib3000mc_write_word(state, 22, 0x463d); in dib3000mc_init()
390 dib3000mc_write_word(state, 120, 0x200f); in dib3000mc_init()
392 dib3000mc_write_word(state, 134, 0); in dib3000mc_init()
395 dib3000mc_write_word(state, 195, 0x10); in dib3000mc_init()
398 dib3000mc_write_word(state, 180, 0x2FF0); in dib3000mc_init()
401 dib3000mc_set_impulse_noise(state, 0, TRANSMISSION_MODE_8K); in dib3000mc_init()
404 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z); in dib3000mc_init()
407 dib3000mc_write_word(state, 769, (1 << 7) ); in dib3000mc_init()
414 struct dib3000mc_state *state = demod->demodulator_priv; in dib3000mc_sleep() local
416 dib3000mc_write_word(state, 1031, 0xFFFF); in dib3000mc_sleep()
417 dib3000mc_write_word(state, 1032, 0xFFFF); in dib3000mc_sleep()
418 dib3000mc_write_word(state, 1033, 0xFFF0); in dib3000mc_sleep()
423 static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam) in dib3000mc_set_adp_cfg() argument
438 dib3000mc_write_word(state, reg, cfg[reg - 129]); in dib3000mc_set_adp_cfg()
441 static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, in dib3000mc_set_channel_cfg() argument
447 dib3000mc_set_bandwidth(state, bw); in dib3000mc_set_channel_cfg()
448 dib3000mc_set_timing(state, ch->transmission_mode, bw, 0); in dib3000mc_set_channel_cfg()
451 dib3000mc_write_word(state, 100, (16 << 6) + 9); in dib3000mc_set_channel_cfg()
454 dib3000mc_write_word(state, 100, (11 << 6) + 6); in dib3000mc_set_channel_cfg()
456 dib3000mc_write_word(state, 100, (16 << 6) + 9); in dib3000mc_set_channel_cfg()
459 dib3000mc_write_word(state, 1027, 0x0800); in dib3000mc_set_channel_cfg()
460 dib3000mc_write_word(state, 1027, 0x0000); in dib3000mc_set_channel_cfg()
463 dib3000mc_write_word(state, 26, 0x6680); in dib3000mc_set_channel_cfg()
464 dib3000mc_write_word(state, 29, 0x1273); in dib3000mc_set_channel_cfg()
465 dib3000mc_write_word(state, 33, 5); in dib3000mc_set_channel_cfg()
466 dib3000mc_set_adp_cfg(state, QAM_16); in dib3000mc_set_channel_cfg()
467 dib3000mc_write_word(state, 133, 15564); in dib3000mc_set_channel_cfg()
469 dib3000mc_write_word(state, 12 , 0x0); in dib3000mc_set_channel_cfg()
470 dib3000mc_write_word(state, 13 , 0x3e8); in dib3000mc_set_channel_cfg()
471 dib3000mc_write_word(state, 14 , 0x0); in dib3000mc_set_channel_cfg()
472 dib3000mc_write_word(state, 15 , 0x3f2); in dib3000mc_set_channel_cfg()
474 dib3000mc_write_word(state, 93,0); in dib3000mc_set_channel_cfg()
475 dib3000mc_write_word(state, 94,0); in dib3000mc_set_channel_cfg()
476 dib3000mc_write_word(state, 95,0); in dib3000mc_set_channel_cfg()
477 dib3000mc_write_word(state, 96,0); in dib3000mc_set_channel_cfg()
478 dib3000mc_write_word(state, 97,0); in dib3000mc_set_channel_cfg()
479 dib3000mc_write_word(state, 98,0); in dib3000mc_set_channel_cfg()
481 dib3000mc_set_impulse_noise(state, 0, ch->transmission_mode); in dib3000mc_set_channel_cfg()
508 dib3000mc_write_word(state, 0, value); in dib3000mc_set_channel_cfg()
509 dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4)); in dib3000mc_set_channel_cfg()
524 dib3000mc_write_word(state, 181, value); in dib3000mc_set_channel_cfg()
540 value |= dib3000mc_read_word(state, 180) & 0x000f; in dib3000mc_set_channel_cfg()
541 dib3000mc_write_word(state, 180, value); in dib3000mc_set_channel_cfg()
544 value = dib3000mc_read_word(state, 0); in dib3000mc_set_channel_cfg()
545 dib3000mc_write_word(state, 0, value | (1 << 9)); in dib3000mc_set_channel_cfg()
546 dib3000mc_write_word(state, 0, value); in dib3000mc_set_channel_cfg()
550 dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->transmission_mode); in dib3000mc_set_channel_cfg()
556 struct dib3000mc_state *state = demod->demodulator_priv; in dib3000mc_autosearch_start() local
573 dib3000mc_set_channel_cfg(state, &schan, 11); in dib3000mc_autosearch_start()
575 reg = dib3000mc_read_word(state, 0); in dib3000mc_autosearch_start()
576 dib3000mc_write_word(state, 0, reg | (1 << 8)); in dib3000mc_autosearch_start()
577 dib3000mc_read_word(state, 511); in dib3000mc_autosearch_start()
578 dib3000mc_write_word(state, 0, reg); in dib3000mc_autosearch_start()
585 struct dib3000mc_state *state = demod->demodulator_priv; in dib3000mc_autosearch_is_irq() local
586 u16 irq_pending = dib3000mc_read_word(state, 511); in dib3000mc_autosearch_is_irq()
600 struct dib3000mc_state *state = demod->demodulator_priv; in dib3000mc_tune() local
603 dib3000mc_set_channel_cfg(state, ch, 0); in dib3000mc_tune()
606 if (state->sfn_workaround_active) { in dib3000mc_tune()
608 dib3000mc_write_word(state, 29, 0x1273); in dib3000mc_tune()
609 dib3000mc_write_word(state, 108, 0x4000); // P_pha3_force_pha_shift in dib3000mc_tune()
611 dib3000mc_write_word(state, 29, 0x1073); in dib3000mc_tune()
612 dib3000mc_write_word(state, 108, 0x0000); // P_pha3_force_pha_shift in dib3000mc_tune()
615 dib3000mc_set_adp_cfg(state, (u8)ch->modulation); in dib3000mc_tune()
617 dib3000mc_write_word(state, 26, 38528); in dib3000mc_tune()
618 dib3000mc_write_word(state, 33, 8); in dib3000mc_tune()
620 dib3000mc_write_word(state, 26, 30336); in dib3000mc_tune()
621 dib3000mc_write_word(state, 33, 6); in dib3000mc_tune()
624 if (dib3000mc_read_word(state, 509) & 0x80) in dib3000mc_tune()
625 dib3000mc_set_timing(state, ch->transmission_mode, in dib3000mc_tune()
642 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_get_frontend() local
643 u16 tps = dib3000mc_read_word(state,458); in dib3000mc_get_frontend()
647 fep->bandwidth_hz = state->current_bandwidth; in dib3000mc_get_frontend()
697 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_set_frontend() local
700 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z); in dib3000mc_set_frontend()
702 state->current_bandwidth = fep->bandwidth_hz; in dib3000mc_set_frontend()
703 dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz)); in dib3000mc_set_frontend()
706 state->sfn_workaround_active = buggy_sfn_workaround; in dib3000mc_set_frontend()
735 dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO); in dib3000mc_set_frontend()
741 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_read_status() local
742 u16 lock = dib3000mc_read_word(state, 509); in dib3000mc_read_status()
762 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_read_ber() local
763 *ber = (dib3000mc_read_word(state, 500) << 16) | dib3000mc_read_word(state, 501); in dib3000mc_read_ber()
769 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_read_unc_blocks() local
770 *unc = dib3000mc_read_word(state, 508); in dib3000mc_read_unc_blocks()
776 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_read_signal_strength() local
777 u16 val = dib3000mc_read_word(state, 392); in dib3000mc_read_signal_strength()
796 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_release() local
797 dibx000_exit_i2c_master(&state->i2c_master); in dib3000mc_release()
798 kfree(state); in dib3000mc_release()
803 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_pid_control() local
804 dib3000mc_write_word(state, 212 + index, onoff ? (1 << 13) | pid : 0); in dib3000mc_pid_control()
811 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_pid_parse() local
812 u16 tmp = dib3000mc_read_word(state, 206) & ~(1 << 4); in dib3000mc_pid_parse()
814 return dib3000mc_write_word(state, 206, tmp); in dib3000mc_pid_parse()
820 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_set_config() local
821 state->cfg = cfg; in dib3000mc_set_config()