255 	int status;  in i2c_write()  local
266 	status = drxk_i2c_transfer(state, &msg, 1);  in i2c_write()
267 	if (status >= 0 && status != 1)  in i2c_write()
268 		status = -EIO;  in i2c_write()
270 	if (status < 0)  in i2c_write()
273 	return status;  in i2c_write()
279 	int status;  in i2c_read()  local
287 	status = drxk_i2c_transfer(state, msgs, 2);  in i2c_read()
288 	if (status != 2) {  in i2c_read()
291 		if (status >= 0)  in i2c_read()
292 			status = -EIO;  in i2c_read()
295 		return status;  in i2c_read()
312 	int status;  in read16_flags()  local
330 	status = i2c_read(state, adr, mm1, len, mm2, 2);  in read16_flags()
331 	if (status < 0)  in read16_flags()
332 		return status;  in read16_flags()
346 	int status;  in read32_flags()  local
364 	status = i2c_read(state, adr, mm1, len, mm2, 4);  in read32_flags()
365 	if (status < 0)  in read32_flags()
366 		return status;  in read32_flags()
442 	int status = 0, blk_size = block_size;  in write_block()  local
478 		status = i2c_write(state, state->demod_address,  in write_block()
480 		if (status < 0) {  in write_block()
489 	return status;  in write_block()
498 	int status;  in power_up_device()  local
504 	status = i2c_read1(state, state->demod_address, &data);  in power_up_device()
505 	if (status < 0) {  in power_up_device()
508 			status = i2c_write(state, state->demod_address,  in power_up_device()
512 			if (status < 0)  in power_up_device()
514 			status = i2c_read1(state, state->demod_address,  in power_up_device()
516 		} while (status < 0 &&  in power_up_device()
518 		if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)  in power_up_device()
523 	status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);  in power_up_device()
524 	if (status < 0)  in power_up_device()
526 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in power_up_device()
527 	if (status < 0)  in power_up_device()
530 	status = write16(state, SIO_CC_PLL_LOCK__A, 1);  in power_up_device()
531 	if (status < 0)  in power_up_device()
537 	if (status < 0)  in power_up_device()
538 		pr_err("Error %d on %s\n", status, __func__);  in power_up_device()
540 	return status;  in power_up_device()
781 	int status = 0;  in drxx_open()  local
788 	status = write16(state, SCU_RAM_GPIO__A,  in drxx_open()
790 	if (status < 0)  in drxx_open()
793 	status = read16(state, SIO_TOP_COMM_KEY__A, &key);  in drxx_open()
794 	if (status < 0)  in drxx_open()
796 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in drxx_open()
797 	if (status < 0)  in drxx_open()
799 	status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);  in drxx_open()
800 	if (status < 0)  in drxx_open()
802 	status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);  in drxx_open()
803 	if (status < 0)  in drxx_open()
805 	status = write16(state, SIO_TOP_COMM_KEY__A, key);  in drxx_open()
807 	if (status < 0)  in drxx_open()
808 		pr_err("Error %d on %s\n", status, __func__);  in drxx_open()
809 	return status;  in drxx_open()
816 	int status;  in get_device_capabilities()  local
823 	status = write16(state, SCU_RAM_GPIO__A,  in get_device_capabilities()
825 	if (status < 0)  in get_device_capabilities()
827 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in get_device_capabilities()
828 	if (status < 0)  in get_device_capabilities()
830 	status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);  in get_device_capabilities()
831 	if (status < 0)  in get_device_capabilities()
833 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in get_device_capabilities()
834 	if (status < 0)  in get_device_capabilities()
861 	status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);  in get_device_capabilities()
862 	if (status < 0)  in get_device_capabilities()
883 		status = -EINVAL;  in get_device_capabilities()
995 		status = -EINVAL;  in get_device_capabilities()
1005 	if (status < 0)  in get_device_capabilities()
1006 		pr_err("Error %d on %s\n", status, __func__);  in get_device_capabilities()
1009 	return status;  in get_device_capabilities()
1014 	int status;  in hi_command()  local
1020 	status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);  in hi_command()
1021 	if (status < 0)  in hi_command()
1039 			status = read16(state, SIO_HI_RA_RAM_CMD__A,  in hi_command()
1041 		} while ((status < 0) && (retry_count < DRXK_MAX_RETRIES)  in hi_command()
1043 		if (status < 0)  in hi_command()
1045 		status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);  in hi_command()
1048 	if (status < 0)  in hi_command()
1049 		pr_err("Error %d on %s\n", status, __func__);  in hi_command()
1051 	return status;  in hi_command()
1056 	int status;  in hi_cfg_command()  local
1062 	status = write16(state, SIO_HI_RA_RAM_PAR_6__A,  in hi_cfg_command()
1064 	if (status < 0)  in hi_cfg_command()
1066 	status = write16(state, SIO_HI_RA_RAM_PAR_5__A,  in hi_cfg_command()
1068 	if (status < 0)  in hi_cfg_command()
1070 	status = write16(state, SIO_HI_RA_RAM_PAR_4__A,  in hi_cfg_command()
1072 	if (status < 0)  in hi_cfg_command()
1074 	status = write16(state, SIO_HI_RA_RAM_PAR_3__A,  in hi_cfg_command()
1076 	if (status < 0)  in hi_cfg_command()
1078 	status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in hi_cfg_command()
1080 	if (status < 0)  in hi_cfg_command()
1082 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,  in hi_cfg_command()
1084 	if (status < 0)  in hi_cfg_command()
1086 	status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);  in hi_cfg_command()
1087 	if (status < 0)  in hi_cfg_command()
1093 	if (status < 0)  in hi_cfg_command()
1094 		pr_err("Error %d on %s\n", status, __func__);  in hi_cfg_command()
1095 	return status;  in hi_cfg_command()
1112 	int status = -1;  in mpegts_configure_pins()  local
1122 	status = write16(state, SCU_RAM_GPIO__A,  in mpegts_configure_pins()
1124 	if (status < 0)  in mpegts_configure_pins()
1128 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in mpegts_configure_pins()
1129 	if (status < 0)  in mpegts_configure_pins()
1134 		status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);  in mpegts_configure_pins()
1135 		if (status < 0)  in mpegts_configure_pins()
1137 		status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);  in mpegts_configure_pins()
1138 		if (status < 0)  in mpegts_configure_pins()
1140 		status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);  in mpegts_configure_pins()
1141 		if (status < 0)  in mpegts_configure_pins()
1143 		status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);  in mpegts_configure_pins()
1144 		if (status < 0)  in mpegts_configure_pins()
1146 		status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);  in mpegts_configure_pins()
1147 		if (status < 0)  in mpegts_configure_pins()
1149 		status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);  in mpegts_configure_pins()
1150 		if (status < 0)  in mpegts_configure_pins()
1152 		status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);  in mpegts_configure_pins()
1153 		if (status < 0)  in mpegts_configure_pins()
1155 		status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);  in mpegts_configure_pins()
1156 		if (status < 0)  in mpegts_configure_pins()
1158 		status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);  in mpegts_configure_pins()
1159 		if (status < 0)  in mpegts_configure_pins()
1161 		status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);  in mpegts_configure_pins()
1162 		if (status < 0)  in mpegts_configure_pins()
1164 		status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);  in mpegts_configure_pins()
1165 		if (status < 0)  in mpegts_configure_pins()
1167 		status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);  in mpegts_configure_pins()
1168 		if (status < 0)  in mpegts_configure_pins()
1179 		status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);  in mpegts_configure_pins()
1180 		if (status < 0)  in mpegts_configure_pins()
1186 		status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);  in mpegts_configure_pins()
1187 		if (status < 0)  in mpegts_configure_pins()
1189 		status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);  in mpegts_configure_pins()
1190 		if (status < 0)  in mpegts_configure_pins()
1195 			status = write16(state, SIO_PDR_MD1_CFG__A,  in mpegts_configure_pins()
1197 			if (status < 0)  in mpegts_configure_pins()
1199 			status = write16(state, SIO_PDR_MD2_CFG__A,  in mpegts_configure_pins()
1201 			if (status < 0)  in mpegts_configure_pins()
1203 			status = write16(state, SIO_PDR_MD3_CFG__A,  in mpegts_configure_pins()
1205 			if (status < 0)  in mpegts_configure_pins()
1207 			status = write16(state, SIO_PDR_MD4_CFG__A,  in mpegts_configure_pins()
1209 			if (status < 0)  in mpegts_configure_pins()
1211 			status = write16(state, SIO_PDR_MD5_CFG__A,  in mpegts_configure_pins()
1213 			if (status < 0)  in mpegts_configure_pins()
1215 			status = write16(state, SIO_PDR_MD6_CFG__A,  in mpegts_configure_pins()
1217 			if (status < 0)  in mpegts_configure_pins()
1219 			status = write16(state, SIO_PDR_MD7_CFG__A,  in mpegts_configure_pins()
1221 			if (status < 0)  in mpegts_configure_pins()
1228 			status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);  in mpegts_configure_pins()
1229 			if (status < 0)  in mpegts_configure_pins()
1231 			status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);  in mpegts_configure_pins()
1232 			if (status < 0)  in mpegts_configure_pins()
1234 			status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);  in mpegts_configure_pins()
1235 			if (status < 0)  in mpegts_configure_pins()
1237 			status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);  in mpegts_configure_pins()
1238 			if (status < 0)  in mpegts_configure_pins()
1240 			status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);  in mpegts_configure_pins()
1241 			if (status < 0)  in mpegts_configure_pins()
1243 			status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);  in mpegts_configure_pins()
1244 			if (status < 0)  in mpegts_configure_pins()
1246 			status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);  in mpegts_configure_pins()
1247 			if (status < 0)  in mpegts_configure_pins()
1250 		status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);  in mpegts_configure_pins()
1251 		if (status < 0)  in mpegts_configure_pins()
1253 		status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);  in mpegts_configure_pins()
1254 		if (status < 0)  in mpegts_configure_pins()
1258 	status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);  in mpegts_configure_pins()
1259 	if (status < 0)  in mpegts_configure_pins()
1262 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in mpegts_configure_pins()
1264 	if (status < 0)  in mpegts_configure_pins()
1265 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_configure_pins()
1266 	return status;  in mpegts_configure_pins()
1280 	int status;  in bl_chain_cmd()  local
1285 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);  in bl_chain_cmd()
1286 	if (status < 0)  in bl_chain_cmd()
1288 	status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);  in bl_chain_cmd()
1289 	if (status < 0)  in bl_chain_cmd()
1291 	status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);  in bl_chain_cmd()
1292 	if (status < 0)  in bl_chain_cmd()
1294 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);  in bl_chain_cmd()
1295 	if (status < 0)  in bl_chain_cmd()
1301 		status = read16(state, SIO_BL_STATUS__A, &bl_status);  in bl_chain_cmd()
1302 		if (status < 0)  in bl_chain_cmd()
1309 		status = -EINVAL;  in bl_chain_cmd()
1313 	if (status < 0)  in bl_chain_cmd()
1314 		pr_err("Error %d on %s\n", status, __func__);  in bl_chain_cmd()
1317 	return status;  in bl_chain_cmd()
1330 	int status = 0;  in download_microcode()  local
1374 		status = write_block(state, address, block_size, p_src);  in download_microcode()
1375 		if (status < 0) {  in download_microcode()
1376 			pr_err("Error %d while loading firmware\n", status);  in download_microcode()
1382 	return status;  in download_microcode()
1387 	int status;  in dvbt_enable_ofdm_token_ring()  local
1400 	status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);  in dvbt_enable_ofdm_token_ring()
1401 	if (status >= 0 && data == desired_status) {  in dvbt_enable_ofdm_token_ring()
1403 		return status;  in dvbt_enable_ofdm_token_ring()
1406 	status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);  in dvbt_enable_ofdm_token_ring()
1410 		status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);  in dvbt_enable_ofdm_token_ring()
1411 		if ((status >= 0 && data == desired_status)  in dvbt_enable_ofdm_token_ring()
1420 	return status;  in dvbt_enable_ofdm_token_ring()
1425 	int status = 0;  in mpegts_stop()  local
1432 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);  in mpegts_stop()
1433 	if (status < 0)  in mpegts_stop()
1436 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);  in mpegts_stop()
1437 	if (status < 0)  in mpegts_stop()
1441 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);  in mpegts_stop()
1442 	if (status < 0)  in mpegts_stop()
1445 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);  in mpegts_stop()
1448 	if (status < 0)  in mpegts_stop()
1449 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_stop()
1451 	return status;  in mpegts_stop()
1462 	int status = -EINVAL;  in scu_command()  local
1473 		pr_err("Error %d on %s\n", status, __func__);  in scu_command()
1474 		return status;  in scu_command()
1494 		status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);  in scu_command()
1495 		if (status < 0)  in scu_command()
1500 		status = -EIO;  in scu_command()
1509 			status = read16(state, SCU_RAM_PARAM_0__A - ii,  in scu_command()
1511 			if (status < 0)  in scu_command()
1540 		status = -EINVAL;  in scu_command()
1545 	if (status < 0)  in scu_command()
1546 		pr_err("Error %d on %s\n", status, __func__);  in scu_command()
1549 	return status;  in scu_command()
1555 	int status;  in set_iqm_af()  local
1560 	status = read16(state, IQM_AF_STDBY__A, &data);  in set_iqm_af()
1561 	if (status < 0)  in set_iqm_af()
1578 	status = write16(state, IQM_AF_STDBY__A, data);  in set_iqm_af()
1581 	if (status < 0)  in set_iqm_af()
1582 		pr_err("Error %d on %s\n", status, __func__);  in set_iqm_af()
1583 	return status;  in set_iqm_af()
1588 	int status = 0;  in ctrl_power_mode()  local
1624 		status = power_up_device(state);  in ctrl_power_mode()
1625 		if (status < 0)  in ctrl_power_mode()
1627 		status = dvbt_enable_ofdm_token_ring(state, true);  in ctrl_power_mode()
1628 		if (status < 0)  in ctrl_power_mode()
1646 			status = mpegts_stop(state);  in ctrl_power_mode()
1647 			if (status < 0)  in ctrl_power_mode()
1649 			status = power_down_dvbt(state, false);  in ctrl_power_mode()
1650 			if (status < 0)  in ctrl_power_mode()
1655 			status = mpegts_stop(state);  in ctrl_power_mode()
1656 			if (status < 0)  in ctrl_power_mode()
1658 			status = power_down_qam(state);  in ctrl_power_mode()
1659 			if (status < 0)  in ctrl_power_mode()
1665 		status = dvbt_enable_ofdm_token_ring(state, false);  in ctrl_power_mode()
1666 		if (status < 0)  in ctrl_power_mode()
1668 		status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);  in ctrl_power_mode()
1669 		if (status < 0)  in ctrl_power_mode()
1671 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in ctrl_power_mode()
1672 		if (status < 0)  in ctrl_power_mode()
1678 			status = hi_cfg_command(state);  in ctrl_power_mode()
1679 			if (status < 0)  in ctrl_power_mode()
1686 	if (status < 0)  in ctrl_power_mode()
1687 		pr_err("Error %d on %s\n", status, __func__);  in ctrl_power_mode()
1689 	return status;  in ctrl_power_mode()
1697 	int status;  in power_down_dvbt()  local
1701 	status = read16(state, SCU_COMM_EXEC__A, &data);  in power_down_dvbt()
1702 	if (status < 0)  in power_down_dvbt()
1706 		status = scu_command(state,  in power_down_dvbt()
1710 		if (status < 0)  in power_down_dvbt()
1713 		status = scu_command(state,  in power_down_dvbt()
1717 		if (status < 0)  in power_down_dvbt()
1722 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in power_down_dvbt()
1723 	if (status < 0)  in power_down_dvbt()
1725 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in power_down_dvbt()
1726 	if (status < 0)  in power_down_dvbt()
1728 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in power_down_dvbt()
1729 	if (status < 0)  in power_down_dvbt()
1733 	status = set_iqm_af(state, false);  in power_down_dvbt()
1734 	if (status < 0)  in power_down_dvbt()
1739 		status = ctrl_power_mode(state, &power_mode);  in power_down_dvbt()
1740 		if (status < 0)  in power_down_dvbt()
1744 	if (status < 0)  in power_down_dvbt()
1745 		pr_err("Error %d on %s\n", status, __func__);  in power_down_dvbt()
1746 	return status;  in power_down_dvbt()
1752 	int status = 0;  in setoperation_mode()  local
1762 	status = write16(state, SCU_RAM_GPIO__A,  in setoperation_mode()
1764 	if (status < 0)  in setoperation_mode()
1776 		status = mpegts_stop(state);  in setoperation_mode()
1777 		if (status < 0)  in setoperation_mode()
1779 		status = power_down_dvbt(state, true);  in setoperation_mode()
1780 		if (status < 0)  in setoperation_mode()
1786 		status = mpegts_stop(state);  in setoperation_mode()
1787 		if (status < 0)  in setoperation_mode()
1789 		status = power_down_qam(state);  in setoperation_mode()
1790 		if (status < 0)  in setoperation_mode()
1796 		status = -EINVAL;  in setoperation_mode()
1807 		status = set_dvbt_standard(state, o_mode);  in setoperation_mode()
1808 		if (status < 0)  in setoperation_mode()
1816 		status = set_qam_standard(state, o_mode);  in setoperation_mode()
1817 		if (status < 0)  in setoperation_mode()
1822 		status = -EINVAL;  in setoperation_mode()
1825 	if (status < 0)  in setoperation_mode()
1826 		pr_err("Error %d on %s\n", status, __func__);  in setoperation_mode()
1827 	return status;  in setoperation_mode()
1833 	int status = -EINVAL;  in start()  local
1854 		status = set_qam(state, i_freqk_hz, offsetk_hz);  in start()
1855 		if (status < 0)  in start()
1861 		status = mpegts_stop(state);  in start()
1862 		if (status < 0)  in start()
1864 		status = set_dvbt(state, i_freqk_hz, offsetk_hz);  in start()
1865 		if (status < 0)  in start()
1867 		status = dvbt_start(state);  in start()
1868 		if (status < 0)  in start()
1876 	if (status < 0)  in start()
1877 		pr_err("Error %d on %s\n", status, __func__);  in start()
1878 	return status;  in start()
1891 	int status = -EINVAL;  in get_lock_status()  local
1905 		status = get_qam_lock_status(state, p_lock_status);  in get_lock_status()
1908 		status = get_dvbt_lock_status(state, p_lock_status);  in get_lock_status()
1914 	if (status < 0)  in get_lock_status()
1915 		pr_err("Error %d on %s\n", status, __func__);  in get_lock_status()
1916 	return status;  in get_lock_status()
1921 	int status;  in mpegts_start()  local
1926 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);  in mpegts_start()
1927 	if (status < 0)  in mpegts_start()
1930 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);  in mpegts_start()
1931 	if (status < 0)  in mpegts_start()
1933 	status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);  in mpegts_start()
1935 	if (status < 0)  in mpegts_start()
1936 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_start()
1937 	return status;  in mpegts_start()
1942 	int status;  in mpegts_dto_init()  local
1947 	status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);  in mpegts_dto_init()
1948 	if (status < 0)  in mpegts_dto_init()
1950 	status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);  in mpegts_dto_init()
1951 	if (status < 0)  in mpegts_dto_init()
1953 	status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);  in mpegts_dto_init()
1954 	if (status < 0)  in mpegts_dto_init()
1956 	status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);  in mpegts_dto_init()
1957 	if (status < 0)  in mpegts_dto_init()
1959 	status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);  in mpegts_dto_init()
1960 	if (status < 0)  in mpegts_dto_init()
1962 	status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);  in mpegts_dto_init()
1963 	if (status < 0)  in mpegts_dto_init()
1965 	status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);  in mpegts_dto_init()
1966 	if (status < 0)  in mpegts_dto_init()
1968 	status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);  in mpegts_dto_init()
1969 	if (status < 0)  in mpegts_dto_init()
1973 	status = write16(state, FEC_OC_OCR_INVERT__A, 0);  in mpegts_dto_init()
1974 	if (status < 0)  in mpegts_dto_init()
1976 	status = write16(state, FEC_OC_SNC_LWM__A, 2);  in mpegts_dto_init()
1977 	if (status < 0)  in mpegts_dto_init()
1979 	status = write16(state, FEC_OC_SNC_HWM__A, 12);  in mpegts_dto_init()
1981 	if (status < 0)  in mpegts_dto_init()
1982 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_dto_init()
1984 	return status;  in mpegts_dto_init()
1990 	int status;  in mpegts_dto_setup()  local
2007 	status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);  in mpegts_dto_setup()
2008 	if (status < 0)  in mpegts_dto_setup()
2010 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);  in mpegts_dto_setup()
2011 	if (status < 0)  in mpegts_dto_setup()
2046 		status = -EINVAL;  in mpegts_dto_setup()
2048 	if (status < 0)  in mpegts_dto_setup()
2090 	status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);  in mpegts_dto_setup()
2091 	if (status < 0)  in mpegts_dto_setup()
2093 	status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);  in mpegts_dto_setup()
2094 	if (status < 0)  in mpegts_dto_setup()
2096 	status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);  in mpegts_dto_setup()
2097 	if (status < 0)  in mpegts_dto_setup()
2099 	status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);  in mpegts_dto_setup()
2100 	if (status < 0)  in mpegts_dto_setup()
2102 	status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);  in mpegts_dto_setup()
2103 	if (status < 0)  in mpegts_dto_setup()
2105 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);  in mpegts_dto_setup()
2106 	if (status < 0)  in mpegts_dto_setup()
2110 	status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);  in mpegts_dto_setup()
2111 	if (status < 0)  in mpegts_dto_setup()
2113 	status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,  in mpegts_dto_setup()
2115 	if (status < 0)  in mpegts_dto_setup()
2117 	status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);  in mpegts_dto_setup()
2119 	if (status < 0)  in mpegts_dto_setup()
2120 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_dto_setup()
2121 	return status;  in mpegts_dto_setup()
2162 	int status = -EINVAL;  in set_agc_rf()  local
2174 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2175 		if (status < 0)  in set_agc_rf()
2178 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2179 		if (status < 0)  in set_agc_rf()
2181 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2182 		if (status < 0)  in set_agc_rf()
2193 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2194 		if (status < 0)  in set_agc_rf()
2198 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);  in set_agc_rf()
2199 		if (status < 0)  in set_agc_rf()
2207 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);  in set_agc_rf()
2208 		if (status < 0)  in set_agc_rf()
2218 			status = -EINVAL;  in set_agc_rf()
2224 			status = write16(state,  in set_agc_rf()
2227 			if (status < 0)  in set_agc_rf()
2232 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,  in set_agc_rf()
2234 		if (status < 0)  in set_agc_rf()
2238 		status = write16(state, SCU_RAM_AGC_RF_MAX__A,  in set_agc_rf()
2240 		if (status < 0)  in set_agc_rf()
2247 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2248 		if (status < 0)  in set_agc_rf()
2251 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2252 		if (status < 0)  in set_agc_rf()
2256 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2257 		if (status < 0)  in set_agc_rf()
2264 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2265 		if (status < 0)  in set_agc_rf()
2269 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);  in set_agc_rf()
2270 		if (status < 0)  in set_agc_rf()
2274 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,  in set_agc_rf()
2276 		if (status < 0)  in set_agc_rf()
2282 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2283 		if (status < 0)  in set_agc_rf()
2286 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2287 		if (status < 0)  in set_agc_rf()
2291 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2292 		if (status < 0)  in set_agc_rf()
2295 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2296 		if (status < 0)  in set_agc_rf()
2301 		status = -EINVAL;  in set_agc_rf()
2305 	if (status < 0)  in set_agc_rf()
2306 		pr_err("Error %d on %s\n", status, __func__);  in set_agc_rf()
2307 	return status;  in set_agc_rf()
2316 	int status = 0;  in set_agc_if()  local
2325 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2326 		if (status < 0)  in set_agc_if()
2329 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2330 		if (status < 0)  in set_agc_if()
2333 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2334 		if (status < 0)  in set_agc_if()
2345 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2346 		if (status < 0)  in set_agc_if()
2350 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);  in set_agc_if()
2351 		if (status < 0)  in set_agc_if()
2358 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);  in set_agc_if()
2359 		if (status < 0)  in set_agc_if()
2369 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in set_agc_if()
2371 		if (status < 0)  in set_agc_if()
2378 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2379 		if (status < 0)  in set_agc_if()
2382 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2383 		if (status < 0)  in set_agc_if()
2386 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2387 		if (status < 0)  in set_agc_if()
2398 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2399 		if (status < 0)  in set_agc_if()
2403 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in set_agc_if()
2405 		if (status < 0)  in set_agc_if()
2412 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2413 		if (status < 0)  in set_agc_if()
2416 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2417 		if (status < 0)  in set_agc_if()
2421 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2422 		if (status < 0)  in set_agc_if()
2425 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2426 		if (status < 0)  in set_agc_if()
2433 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);  in set_agc_if()
2435 	if (status < 0)  in set_agc_if()
2436 		pr_err("Error %d on %s\n", status, __func__);  in set_agc_if()
2437 	return status;  in set_agc_if()
2443 	int status = 0;  in get_qam_signal_to_noise()  local
2455 	status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);  in get_qam_signal_to_noise()
2456 	if (status < 0) {  in get_qam_signal_to_noise()
2457 		pr_err("Error %d on %s\n", status, __func__);  in get_qam_signal_to_noise()
2486 	return status;  in get_qam_signal_to_noise()
2492 	int status;  in get_dvbt_signal_to_noise()  local
2509 	status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,  in get_dvbt_signal_to_noise()
2511 	if (status < 0)  in get_dvbt_signal_to_noise()
2513 	status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,  in get_dvbt_signal_to_noise()
2515 	if (status < 0)  in get_dvbt_signal_to_noise()
2517 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,  in get_dvbt_signal_to_noise()
2519 	if (status < 0)  in get_dvbt_signal_to_noise()
2521 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,  in get_dvbt_signal_to_noise()
2523 	if (status < 0)  in get_dvbt_signal_to_noise()
2531 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data);  in get_dvbt_signal_to_noise()
2532 	if (status < 0)  in get_dvbt_signal_to_noise()
2540 	status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,  in get_dvbt_signal_to_noise()
2542 	if (status < 0)  in get_dvbt_signal_to_noise()
2588 	if (status < 0)  in get_dvbt_signal_to_noise()
2589 		pr_err("Error %d on %s\n", status, __func__);  in get_dvbt_signal_to_noise()
2590 	return status;  in get_dvbt_signal_to_noise()
2614 	int status = 0;
2645 		status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2646 		if (status < 0)
2648 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2650 		if (status < 0)
2654 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2656 		if (status < 0)
2680 	int status = 0;
2690 		status = get_qam_signal_to_noise(state, &signal_to_noise);
2691 		if (status < 0)
2722 	return status;
2757 	int status = -EINVAL;  in ConfigureI2CBridge()  local
2769 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,  in ConfigureI2CBridge()
2771 	if (status < 0)  in ConfigureI2CBridge()
2774 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in ConfigureI2CBridge()
2776 		if (status < 0)  in ConfigureI2CBridge()
2779 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in ConfigureI2CBridge()
2781 		if (status < 0)  in ConfigureI2CBridge()
2785 	status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);  in ConfigureI2CBridge()
2788 	if (status < 0)  in ConfigureI2CBridge()
2789 		pr_err("Error %d on %s\n", status, __func__);  in ConfigureI2CBridge()
2790 	return status;  in ConfigureI2CBridge()
2796 	int status = -EINVAL;  in set_pre_saw()  local
2804 	status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);  in set_pre_saw()
2806 	if (status < 0)  in set_pre_saw()
2807 		pr_err("Error %d on %s\n", status, __func__);  in set_pre_saw()
2808 	return status;  in set_pre_saw()
2817 	int status;  in bl_direct_cmd()  local
2823 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);  in bl_direct_cmd()
2824 	if (status < 0)  in bl_direct_cmd()
2826 	status = write16(state, SIO_BL_TGT_HDR__A, blockbank);  in bl_direct_cmd()
2827 	if (status < 0)  in bl_direct_cmd()
2829 	status = write16(state, SIO_BL_TGT_ADDR__A, offset);  in bl_direct_cmd()
2830 	if (status < 0)  in bl_direct_cmd()
2832 	status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);  in bl_direct_cmd()
2833 	if (status < 0)  in bl_direct_cmd()
2835 	status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);  in bl_direct_cmd()
2836 	if (status < 0)  in bl_direct_cmd()
2838 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);  in bl_direct_cmd()
2839 	if (status < 0)  in bl_direct_cmd()
2844 		status = read16(state, SIO_BL_STATUS__A, &bl_status);  in bl_direct_cmd()
2845 		if (status < 0)  in bl_direct_cmd()
2850 		status = -EINVAL;  in bl_direct_cmd()
2854 	if (status < 0)  in bl_direct_cmd()
2855 		pr_err("Error %d on %s\n", status, __func__);  in bl_direct_cmd()
2858 	return status;  in bl_direct_cmd()
2865 	int status;  in adc_sync_measurement()  local
2870 	status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);  in adc_sync_measurement()
2871 	if (status < 0)  in adc_sync_measurement()
2873 	status = write16(state, IQM_AF_START_LOCK__A, 1);  in adc_sync_measurement()
2874 	if (status < 0)  in adc_sync_measurement()
2878 	status = read16(state, IQM_AF_PHASE0__A, &data);  in adc_sync_measurement()
2879 	if (status < 0)  in adc_sync_measurement()
2883 	status = read16(state, IQM_AF_PHASE1__A, &data);  in adc_sync_measurement()
2884 	if (status < 0)  in adc_sync_measurement()
2888 	status = read16(state, IQM_AF_PHASE2__A, &data);  in adc_sync_measurement()
2889 	if (status < 0)  in adc_sync_measurement()
2895 	if (status < 0)  in adc_sync_measurement()
2896 		pr_err("Error %d on %s\n", status, __func__);  in adc_sync_measurement()
2897 	return status;  in adc_sync_measurement()
2903 	int status;  in adc_synchronization()  local
2907 	status = adc_sync_measurement(state, &count);  in adc_synchronization()
2908 	if (status < 0)  in adc_synchronization()
2915 		status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);  in adc_synchronization()
2916 		if (status < 0)  in adc_synchronization()
2928 		status = write16(state, IQM_AF_CLKNEG__A, clk_neg);  in adc_synchronization()
2929 		if (status < 0)  in adc_synchronization()
2931 		status = adc_sync_measurement(state, &count);  in adc_synchronization()
2932 		if (status < 0)  in adc_synchronization()
2937 		status = -EINVAL;  in adc_synchronization()
2939 	if (status < 0)  in adc_synchronization()
2940 		pr_err("Error %d on %s\n", status, __func__);  in adc_synchronization()
2941 	return status;  in adc_synchronization()
2954 	int status;  in set_frequency_shifter()  local
3003 	status = write32(state, IQM_FS_RATE_OFS_LO__A,  in set_frequency_shifter()
3005 	if (status < 0)  in set_frequency_shifter()
3006 		pr_err("Error %d on %s\n", status, __func__);  in set_frequency_shifter()
3007 	return status;  in set_frequency_shifter()
3029 	int status = 0;  in init_agc()  local
3062 	status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,  in init_agc()
3064 	if (status < 0)  in init_agc()
3067 	status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);  in init_agc()
3068 	if (status < 0)  in init_agc()
3070 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);  in init_agc()
3071 	if (status < 0)  in init_agc()
3073 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);  in init_agc()
3074 	if (status < 0)  in init_agc()
3076 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);  in init_agc()
3077 	if (status < 0)  in init_agc()
3079 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,  in init_agc()
3081 	if (status < 0)  in init_agc()
3083 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in init_agc()
3085 	if (status < 0)  in init_agc()
3087 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);  in init_agc()
3088 	if (status < 0)  in init_agc()
3090 	status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);  in init_agc()
3091 	if (status < 0)  in init_agc()
3093 	status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);  in init_agc()
3094 	if (status < 0)  in init_agc()
3096 	status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);  in init_agc()
3097 	if (status < 0)  in init_agc()
3099 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);  in init_agc()
3100 	if (status < 0)  in init_agc()
3102 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);  in init_agc()
3103 	if (status < 0)  in init_agc()
3106 	status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,  in init_agc()
3108 	if (status < 0)  in init_agc()
3110 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,  in init_agc()
3112 	if (status < 0)  in init_agc()
3114 	status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);  in init_agc()
3115 	if (status < 0)  in init_agc()
3118 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);  in init_agc()
3119 	if (status < 0)  in init_agc()
3121 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);  in init_agc()
3122 	if (status < 0)  in init_agc()
3124 	status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);  in init_agc()
3125 	if (status < 0)  in init_agc()
3128 	status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);  in init_agc()
3129 	if (status < 0)  in init_agc()
3131 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);  in init_agc()
3132 	if (status < 0)  in init_agc()
3134 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);  in init_agc()
3135 	if (status < 0)  in init_agc()
3137 	status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);  in init_agc()
3138 	if (status < 0)  in init_agc()
3140 	status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);  in init_agc()
3141 	if (status < 0)  in init_agc()
3143 	status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);  in init_agc()
3144 	if (status < 0)  in init_agc()
3146 	status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);  in init_agc()
3147 	if (status < 0)  in init_agc()
3149 	status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);  in init_agc()
3150 	if (status < 0)  in init_agc()
3152 	status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);  in init_agc()
3153 	if (status < 0)  in init_agc()
3155 	status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);  in init_agc()
3156 	if (status < 0)  in init_agc()
3158 	status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);  in init_agc()
3159 	if (status < 0)  in init_agc()
3161 	status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);  in init_agc()
3162 	if (status < 0)  in init_agc()
3164 	status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);  in init_agc()
3165 	if (status < 0)  in init_agc()
3167 	status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);  in init_agc()
3168 	if (status < 0)  in init_agc()
3170 	status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);  in init_agc()
3171 	if (status < 0)  in init_agc()
3173 	status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);  in init_agc()
3174 	if (status < 0)  in init_agc()
3176 	status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);  in init_agc()
3177 	if (status < 0)  in init_agc()
3179 	status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);  in init_agc()
3180 	if (status < 0)  in init_agc()
3182 	status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);  in init_agc()
3183 	if (status < 0)  in init_agc()
3187 	status = read16(state, SCU_RAM_AGC_KI__A, &data);  in init_agc()
3188 	if (status < 0)  in init_agc()
3197 	status = write16(state, SCU_RAM_AGC_KI__A, data);  in init_agc()
3199 	if (status < 0)  in init_agc()
3200 		pr_err("Error %d on %s\n", status, __func__);  in init_agc()
3201 	return status;  in init_agc()
3206 	int status;  in dvbtqam_get_acc_pkt_err()  local
3210 		status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);  in dvbtqam_get_acc_pkt_err()
3212 		status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,  in dvbtqam_get_acc_pkt_err()
3214 	if (status < 0)  in dvbtqam_get_acc_pkt_err()
3215 		pr_err("Error %d on %s\n", status, __func__);  in dvbtqam_get_acc_pkt_err()
3216 	return status;  in dvbtqam_get_acc_pkt_err()
3228 	int status;  in dvbt_sc_command()  local
3231 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);  in dvbt_sc_command()
3234 		status = -EINVAL;  in dvbt_sc_command()
3236 	if (status < 0)  in dvbt_sc_command()
3243 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);  in dvbt_sc_command()
3246 	if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))  in dvbt_sc_command()
3255 		status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);  in dvbt_sc_command()
3256 		if (status < 0)  in dvbt_sc_command()
3265 	status = 0;  in dvbt_sc_command()
3274 		status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);  in dvbt_sc_command()
3278 		status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);  in dvbt_sc_command()
3283 		status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);  in dvbt_sc_command()
3287 		status = -EINVAL;  in dvbt_sc_command()
3289 	if (status < 0)  in dvbt_sc_command()
3296 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);  in dvbt_sc_command()
3299 	if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))  in dvbt_sc_command()
3303 	status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);  in dvbt_sc_command()
3306 		status = -EINVAL;  in dvbt_sc_command()
3308 	if (status < 0)  in dvbt_sc_command()
3320 		status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));  in dvbt_sc_command()
3331 		status = -EINVAL;  in dvbt_sc_command()
3335 	if (status < 0)  in dvbt_sc_command()
3336 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_sc_command()
3337 	return status;  in dvbt_sc_command()
3343 	int status;  in power_up_dvbt()  local
3346 	status = ctrl_power_mode(state, &power_mode);  in power_up_dvbt()
3347 	if (status < 0)  in power_up_dvbt()
3348 		pr_err("Error %d on %s\n", status, __func__);  in power_up_dvbt()
3349 	return status;  in power_up_dvbt()
3354 	int status;  in dvbt_ctrl_set_inc_enable()  local
3358 		status = write16(state, IQM_CF_BYPASSDET__A, 0);  in dvbt_ctrl_set_inc_enable()
3360 		status = write16(state, IQM_CF_BYPASSDET__A, 1);  in dvbt_ctrl_set_inc_enable()
3361 	if (status < 0)  in dvbt_ctrl_set_inc_enable()
3362 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_inc_enable()
3363 	return status;  in dvbt_ctrl_set_inc_enable()
3370 	int status;  in dvbt_ctrl_set_fr_enable()  local
3375 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,  in dvbt_ctrl_set_fr_enable()
3379 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);  in dvbt_ctrl_set_fr_enable()
3381 	if (status < 0)  in dvbt_ctrl_set_fr_enable()
3382 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_fr_enable()
3384 	return status;  in dvbt_ctrl_set_fr_enable()
3391 	int status;  in dvbt_ctrl_set_echo_threshold()  local
3394 	status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);  in dvbt_ctrl_set_echo_threshold()
3395 	if (status < 0)  in dvbt_ctrl_set_echo_threshold()
3415 	status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);  in dvbt_ctrl_set_echo_threshold()
3417 	if (status < 0)  in dvbt_ctrl_set_echo_threshold()
3418 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_echo_threshold()
3419 	return status;  in dvbt_ctrl_set_echo_threshold()
3425 	int status = -EINVAL;  in dvbt_ctrl_set_sqi_speed()  local
3437 	status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,  in dvbt_ctrl_set_sqi_speed()
3440 	if (status < 0)  in dvbt_ctrl_set_sqi_speed()
3441 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_sqi_speed()
3442 	return status;  in dvbt_ctrl_set_sqi_speed()
3457 	int status;  in dvbt_activate_presets()  local
3465 	status = dvbt_ctrl_set_inc_enable(state, &setincenable);  in dvbt_activate_presets()
3466 	if (status < 0)  in dvbt_activate_presets()
3468 	status = dvbt_ctrl_set_fr_enable(state, &setfrenable);  in dvbt_activate_presets()
3469 	if (status < 0)  in dvbt_activate_presets()
3471 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);  in dvbt_activate_presets()
3472 	if (status < 0)  in dvbt_activate_presets()
3474 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);  in dvbt_activate_presets()
3475 	if (status < 0)  in dvbt_activate_presets()
3477 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,  in dvbt_activate_presets()
3480 	if (status < 0)  in dvbt_activate_presets()
3481 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_activate_presets()
3482 	return status;  in dvbt_activate_presets()
3500 	int status;  in set_dvbt_standard()  local
3508 	status = scu_command(state,  in set_dvbt_standard()
3512 	if (status < 0)  in set_dvbt_standard()
3516 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt_standard()
3519 	if (status < 0)  in set_dvbt_standard()
3523 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in set_dvbt_standard()
3524 	if (status < 0)  in set_dvbt_standard()
3526 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in set_dvbt_standard()
3527 	if (status < 0)  in set_dvbt_standard()
3529 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in set_dvbt_standard()
3530 	if (status < 0)  in set_dvbt_standard()
3535 	status = write16(state, IQM_AF_UPD_SEL__A, 1);  in set_dvbt_standard()
3536 	if (status < 0)  in set_dvbt_standard()
3539 	status = write16(state, IQM_AF_CLP_LEN__A, 0);  in set_dvbt_standard()
3540 	if (status < 0)  in set_dvbt_standard()
3543 	status = write16(state, IQM_AF_SNS_LEN__A, 0);  in set_dvbt_standard()
3544 	if (status < 0)  in set_dvbt_standard()
3547 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);  in set_dvbt_standard()
3548 	if (status < 0)  in set_dvbt_standard()
3550 	status = set_iqm_af(state, true);  in set_dvbt_standard()
3551 	if (status < 0)  in set_dvbt_standard()
3554 	status = write16(state, IQM_AF_AGC_RF__A, 0);  in set_dvbt_standard()
3555 	if (status < 0)  in set_dvbt_standard()
3559 	status = write16(state, IQM_AF_INC_LCT__A, 0);	/* crunch in IQM_CF */  in set_dvbt_standard()
3560 	if (status < 0)  in set_dvbt_standard()
3562 	status = write16(state, IQM_CF_DET_LCT__A, 0);	/* detect in IQM_CF */  in set_dvbt_standard()
3563 	if (status < 0)  in set_dvbt_standard()
3565 	status = write16(state, IQM_CF_WND_LEN__A, 3);	/* peak detector window length */  in set_dvbt_standard()
3566 	if (status < 0)  in set_dvbt_standard()
3569 	status = write16(state, IQM_RC_STRETCH__A, 16);  in set_dvbt_standard()
3570 	if (status < 0)  in set_dvbt_standard()
3572 	status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */  in set_dvbt_standard()
3573 	if (status < 0)  in set_dvbt_standard()
3575 	status = write16(state, IQM_CF_DS_ENA__A, 0x4);	/* decimate output 2 */  in set_dvbt_standard()
3576 	if (status < 0)  in set_dvbt_standard()
3578 	status = write16(state, IQM_CF_SCALE__A, 1600);  in set_dvbt_standard()
3579 	if (status < 0)  in set_dvbt_standard()
3581 	status = write16(state, IQM_CF_SCALE_SH__A, 0);  in set_dvbt_standard()
3582 	if (status < 0)  in set_dvbt_standard()
3586 	status = write16(state, IQM_AF_CLP_TH__A, 448);  in set_dvbt_standard()
3587 	if (status < 0)  in set_dvbt_standard()
3589 	status = write16(state, IQM_CF_DATATH__A, 495);	/* crunching threshold */  in set_dvbt_standard()
3590 	if (status < 0)  in set_dvbt_standard()
3593 	status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,  in set_dvbt_standard()
3595 	if (status < 0)  in set_dvbt_standard()
3598 	status = write16(state, IQM_CF_PKDTH__A, 2);	/* peak detector threshold */  in set_dvbt_standard()
3599 	if (status < 0)  in set_dvbt_standard()
3601 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);  in set_dvbt_standard()
3602 	if (status < 0)  in set_dvbt_standard()
3605 	status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);  in set_dvbt_standard()
3606 	if (status < 0)  in set_dvbt_standard()
3608 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);  in set_dvbt_standard()
3609 	if (status < 0)  in set_dvbt_standard()
3613 	status = adc_synchronization(state);  in set_dvbt_standard()
3614 	if (status < 0)  in set_dvbt_standard()
3616 	status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);  in set_dvbt_standard()
3617 	if (status < 0)  in set_dvbt_standard()
3621 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_dvbt_standard()
3622 	if (status < 0)  in set_dvbt_standard()
3625 	status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);  in set_dvbt_standard()
3626 	if (status < 0)  in set_dvbt_standard()
3628 	status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);  in set_dvbt_standard()
3629 	if (status < 0)  in set_dvbt_standard()
3633 	status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);  in set_dvbt_standard()
3634 	if (status < 0)  in set_dvbt_standard()
3637 	status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);  in set_dvbt_standard()
3638 	if (status < 0)  in set_dvbt_standard()
3642 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_dvbt_standard()
3643 	if (status < 0)  in set_dvbt_standard()
3648 		status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,  in set_dvbt_standard()
3650 		if (status < 0)  in set_dvbt_standard()
3656 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);  in set_dvbt_standard()
3657 	if (status < 0)  in set_dvbt_standard()
3659 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);  in set_dvbt_standard()
3660 	if (status < 0)  in set_dvbt_standard()
3665 	status = write16(state, FEC_DI_INPUT_CTL__A, 1);	/* OFDM input */  in set_dvbt_standard()
3666 	if (status < 0)  in set_dvbt_standard()
3671 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);  in set_dvbt_standard()
3672 	if (status < 0)  in set_dvbt_standard()
3675 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);  in set_dvbt_standard()
3676 	if (status < 0)  in set_dvbt_standard()
3679 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);  in set_dvbt_standard()
3680 	if (status < 0)  in set_dvbt_standard()
3684 	status = mpegts_dto_setup(state, OM_DVBT);  in set_dvbt_standard()
3685 	if (status < 0)  in set_dvbt_standard()
3688 	status = dvbt_activate_presets(state);  in set_dvbt_standard()
3689 	if (status < 0)  in set_dvbt_standard()
3693 	if (status < 0)  in set_dvbt_standard()
3694 		pr_err("Error %d on %s\n", status, __func__);  in set_dvbt_standard()
3695 	return status;  in set_dvbt_standard()
3707 	int status;  in dvbt_start()  local
3714 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,  in dvbt_start()
3717 	if (status < 0)  in dvbt_start()
3720 	status = mpegts_start(state);  in dvbt_start()
3721 	if (status < 0)  in dvbt_start()
3723 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);  in dvbt_start()
3724 	if (status < 0)  in dvbt_start()
3727 	if (status < 0)  in dvbt_start()
3728 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_start()
3729 	return status;  in dvbt_start()
3750 	int status;  in set_dvbt()  local
3755 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt()
3758 	if (status < 0)  in set_dvbt()
3762 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_dvbt()
3763 	if (status < 0)  in set_dvbt()
3767 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in set_dvbt()
3768 	if (status < 0)  in set_dvbt()
3770 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in set_dvbt()
3771 	if (status < 0)  in set_dvbt()
3776 	status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);  in set_dvbt()
3777 	if (status < 0)  in set_dvbt()
3869 		status = -EINVAL;  in set_dvbt()
3875 	status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);  in set_dvbt()
3876 	if (status < 0)  in set_dvbt()
3922 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3924 		if (status < 0)  in set_dvbt()
3927 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3929 		if (status < 0)  in set_dvbt()
3931 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3933 		if (status < 0)  in set_dvbt()
3935 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3937 		if (status < 0)  in set_dvbt()
3939 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3941 		if (status < 0)  in set_dvbt()
3946 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3948 		if (status < 0)  in set_dvbt()
3951 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3953 		if (status < 0)  in set_dvbt()
3955 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3957 		if (status < 0)  in set_dvbt()
3959 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3961 		if (status < 0)  in set_dvbt()
3963 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3965 		if (status < 0)  in set_dvbt()
3970 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3972 		if (status < 0)  in set_dvbt()
3975 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3977 		if (status < 0)  in set_dvbt()
3979 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3981 		if (status < 0)  in set_dvbt()
3983 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3985 		if (status < 0)  in set_dvbt()
3987 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3989 		if (status < 0)  in set_dvbt()
3993 		status = -EINVAL;  in set_dvbt()
4024 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);  in set_dvbt()
4025 	if (status < 0)  in set_dvbt()
4031 	status = dvbt_set_frequency_shift(demod, channel, tuner_offset);  in set_dvbt()
4032 	if (status < 0)  in set_dvbt()
4035 	status = set_frequency_shifter(state, intermediate_freqk_hz,  in set_dvbt()
4037 	if (status < 0)  in set_dvbt()
4043 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_dvbt()
4044 	if (status < 0)  in set_dvbt()
4048 	status = write16(state, OFDM_SC_COMM_STATE__A, 0);  in set_dvbt()
4049 	if (status < 0)  in set_dvbt()
4051 	status = write16(state, OFDM_SC_COMM_EXEC__A, 1);  in set_dvbt()
4052 	if (status < 0)  in set_dvbt()
4056 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt()
4059 	if (status < 0)  in set_dvbt()
4068 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,  in set_dvbt()
4070 	if (status < 0)  in set_dvbt()
4074 		status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);  in set_dvbt()
4076 	if (status < 0)  in set_dvbt()
4077 		pr_err("Error %d on %s\n", status, __func__);  in set_dvbt()
4079 	return status;  in set_dvbt()
4094 	int status;  in get_dvbt_lock_status()  local
4108 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);  in get_dvbt_lock_status()
4109 	if (status < 0)  in get_dvbt_lock_status()
4114 	status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);  in get_dvbt_lock_status()
4115 	if (status < 0)  in get_dvbt_lock_status()
4127 	if (status < 0)  in get_dvbt_lock_status()
4128 		pr_err("Error %d on %s\n", status, __func__);  in get_dvbt_lock_status()
4130 	return status;  in get_dvbt_lock_status()
4136 	int status;  in power_up_qam()  local
4139 	status = ctrl_power_mode(state, &power_mode);  in power_up_qam()
4140 	if (status < 0)  in power_up_qam()
4141 		pr_err("Error %d on %s\n", status, __func__);  in power_up_qam()
4143 	return status;  in power_up_qam()
4152 	int status = 0;  in power_down_qam()  local
4155 	status = read16(state, SCU_COMM_EXEC__A, &data);  in power_down_qam()
4156 	if (status < 0)  in power_down_qam()
4164 		status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);  in power_down_qam()
4165 		if (status < 0)  in power_down_qam()
4167 		status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in power_down_qam()
4170 		if (status < 0)  in power_down_qam()
4174 	status = set_iqm_af(state, false);  in power_down_qam()
4177 	if (status < 0)  in power_down_qam()
4178 		pr_err("Error %d on %s\n", status, __func__);  in power_down_qam()
4180 	return status;  in power_down_qam()
4204 	int status = 0;  in set_qam_measurement()  local
4232 		status = -EINVAL;  in set_qam_measurement()
4234 	if (status < 0)  in set_qam_measurement()
4248 		status = -EINVAL;  in set_qam_measurement()
4249 		if (status < 0)  in set_qam_measurement()
4257 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);  in set_qam_measurement()
4258 	if (status < 0)  in set_qam_measurement()
4260 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,  in set_qam_measurement()
4262 	if (status < 0)  in set_qam_measurement()
4264 	status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);  in set_qam_measurement()
4266 	if (status < 0)  in set_qam_measurement()
4267 		pr_err("Error %d on %s\n", status, __func__);  in set_qam_measurement()
4268 	return status;  in set_qam_measurement()
4273 	int status = 0;  in set_qam16()  local
4278 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);  in set_qam16()
4279 	if (status < 0)  in set_qam16()
4281 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);  in set_qam16()
4282 	if (status < 0)  in set_qam16()
4284 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);  in set_qam16()
4285 	if (status < 0)  in set_qam16()
4287 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);  in set_qam16()
4288 	if (status < 0)  in set_qam16()
4290 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);  in set_qam16()
4291 	if (status < 0)  in set_qam16()
4293 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);  in set_qam16()
4294 	if (status < 0)  in set_qam16()
4297 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);  in set_qam16()
4298 	if (status < 0)  in set_qam16()
4300 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);  in set_qam16()
4301 	if (status < 0)  in set_qam16()
4303 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);  in set_qam16()
4304 	if (status < 0)  in set_qam16()
4306 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);  in set_qam16()
4307 	if (status < 0)  in set_qam16()
4309 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);  in set_qam16()
4310 	if (status < 0)  in set_qam16()
4312 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam16()
4313 	if (status < 0)  in set_qam16()
4316 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam16()
4317 	if (status < 0)  in set_qam16()
4319 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam16()
4320 	if (status < 0)  in set_qam16()
4322 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam16()
4323 	if (status < 0)  in set_qam16()
4327 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam16()
4329 	if (status < 0)  in set_qam16()
4333 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam16()
4334 	if (status < 0)  in set_qam16()
4336 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam16()
4337 	if (status < 0)  in set_qam16()
4339 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam16()
4340 	if (status < 0)  in set_qam16()
4342 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam16()
4343 	if (status < 0)  in set_qam16()
4345 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam16()
4346 	if (status < 0)  in set_qam16()
4348 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam16()
4349 	if (status < 0)  in set_qam16()
4351 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam16()
4352 	if (status < 0)  in set_qam16()
4354 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam16()
4355 	if (status < 0)  in set_qam16()
4358 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam16()
4359 	if (status < 0)  in set_qam16()
4361 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);  in set_qam16()
4362 	if (status < 0)  in set_qam16()
4364 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);  in set_qam16()
4365 	if (status < 0)  in set_qam16()
4367 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam16()
4368 	if (status < 0)  in set_qam16()
4370 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);  in set_qam16()
4371 	if (status < 0)  in set_qam16()
4373 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam16()
4374 	if (status < 0)  in set_qam16()
4376 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam16()
4377 	if (status < 0)  in set_qam16()
4379 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);  in set_qam16()
4380 	if (status < 0)  in set_qam16()
4382 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);  in set_qam16()
4383 	if (status < 0)  in set_qam16()
4385 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam16()
4386 	if (status < 0)  in set_qam16()
4388 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam16()
4389 	if (status < 0)  in set_qam16()
4391 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam16()
4392 	if (status < 0)  in set_qam16()
4398 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);  in set_qam16()
4399 	if (status < 0)  in set_qam16()
4401 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);  in set_qam16()
4402 	if (status < 0)  in set_qam16()
4404 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);  in set_qam16()
4405 	if (status < 0)  in set_qam16()
4407 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);  in set_qam16()
4408 	if (status < 0)  in set_qam16()
4410 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);  in set_qam16()
4411 	if (status < 0)  in set_qam16()
4413 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);  in set_qam16()
4414 	if (status < 0)  in set_qam16()
4417 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam16()
4418 	if (status < 0)  in set_qam16()
4420 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam16()
4421 	if (status < 0)  in set_qam16()
4423 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);  in set_qam16()
4424 	if (status < 0)  in set_qam16()
4430 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);  in set_qam16()
4431 	if (status < 0)  in set_qam16()
4433 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);  in set_qam16()
4434 	if (status < 0)  in set_qam16()
4436 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);  in set_qam16()
4437 	if (status < 0)  in set_qam16()
4439 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);  in set_qam16()
4440 	if (status < 0)  in set_qam16()
4442 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);  in set_qam16()
4443 	if (status < 0)  in set_qam16()
4445 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);  in set_qam16()
4446 	if (status < 0)  in set_qam16()
4448 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);  in set_qam16()
4449 	if (status < 0)  in set_qam16()
4453 	if (status < 0)  in set_qam16()
4454 		pr_err("Error %d on %s\n", status, __func__);  in set_qam16()
4455 	return status;  in set_qam16()
4467 	int status = 0;  in set_qam32()  local
4473 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);  in set_qam32()
4474 	if (status < 0)  in set_qam32()
4476 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);  in set_qam32()
4477 	if (status < 0)  in set_qam32()
4479 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);  in set_qam32()
4480 	if (status < 0)  in set_qam32()
4482 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);  in set_qam32()
4483 	if (status < 0)  in set_qam32()
4485 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);  in set_qam32()
4486 	if (status < 0)  in set_qam32()
4488 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);  in set_qam32()
4489 	if (status < 0)  in set_qam32()
4493 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);  in set_qam32()
4494 	if (status < 0)  in set_qam32()
4496 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);  in set_qam32()
4497 	if (status < 0)  in set_qam32()
4499 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);  in set_qam32()
4500 	if (status < 0)  in set_qam32()
4502 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);  in set_qam32()
4503 	if (status < 0)  in set_qam32()
4505 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);  in set_qam32()
4506 	if (status < 0)  in set_qam32()
4508 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam32()
4509 	if (status < 0)  in set_qam32()
4512 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);  in set_qam32()
4513 	if (status < 0)  in set_qam32()
4515 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);  in set_qam32()
4516 	if (status < 0)  in set_qam32()
4518 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam32()
4519 	if (status < 0)  in set_qam32()
4524 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam32()
4526 	if (status < 0)  in set_qam32()
4532 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam32()
4533 	if (status < 0)  in set_qam32()
4535 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam32()
4536 	if (status < 0)  in set_qam32()
4538 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam32()
4539 	if (status < 0)  in set_qam32()
4541 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam32()
4542 	if (status < 0)  in set_qam32()
4544 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam32()
4545 	if (status < 0)  in set_qam32()
4547 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam32()
4548 	if (status < 0)  in set_qam32()
4550 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam32()
4551 	if (status < 0)  in set_qam32()
4553 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam32()
4554 	if (status < 0)  in set_qam32()
4557 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam32()
4558 	if (status < 0)  in set_qam32()
4560 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);  in set_qam32()
4561 	if (status < 0)  in set_qam32()
4563 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);  in set_qam32()
4564 	if (status < 0)  in set_qam32()
4566 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam32()
4567 	if (status < 0)  in set_qam32()
4569 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);  in set_qam32()
4570 	if (status < 0)  in set_qam32()
4572 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam32()
4573 	if (status < 0)  in set_qam32()
4575 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam32()
4576 	if (status < 0)  in set_qam32()
4578 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);  in set_qam32()
4579 	if (status < 0)  in set_qam32()
4581 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);  in set_qam32()
4582 	if (status < 0)  in set_qam32()
4584 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam32()
4585 	if (status < 0)  in set_qam32()
4587 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam32()
4588 	if (status < 0)  in set_qam32()
4590 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);  in set_qam32()
4591 	if (status < 0)  in set_qam32()
4597 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);  in set_qam32()
4598 	if (status < 0)  in set_qam32()
4600 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);  in set_qam32()
4601 	if (status < 0)  in set_qam32()
4603 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam32()
4604 	if (status < 0)  in set_qam32()
4606 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam32()
4607 	if (status < 0)  in set_qam32()
4609 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);  in set_qam32()
4610 	if (status < 0)  in set_qam32()
4612 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);  in set_qam32()
4613 	if (status < 0)  in set_qam32()
4616 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam32()
4617 	if (status < 0)  in set_qam32()
4619 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam32()
4620 	if (status < 0)  in set_qam32()
4622 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);  in set_qam32()
4623 	if (status < 0)  in set_qam32()
4629 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);  in set_qam32()
4630 	if (status < 0)  in set_qam32()
4632 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);  in set_qam32()
4633 	if (status < 0)  in set_qam32()
4635 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);  in set_qam32()
4636 	if (status < 0)  in set_qam32()
4638 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);  in set_qam32()
4639 	if (status < 0)  in set_qam32()
4641 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);  in set_qam32()
4642 	if (status < 0)  in set_qam32()
4644 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);  in set_qam32()
4645 	if (status < 0)  in set_qam32()
4647 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);  in set_qam32()
4649 	if (status < 0)  in set_qam32()
4650 		pr_err("Error %d on %s\n", status, __func__);  in set_qam32()
4651 	return status;  in set_qam32()
4663 	int status = 0;  in set_qam64()  local
4668 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);  in set_qam64()
4669 	if (status < 0)  in set_qam64()
4671 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);  in set_qam64()
4672 	if (status < 0)  in set_qam64()
4674 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);  in set_qam64()
4675 	if (status < 0)  in set_qam64()
4677 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);  in set_qam64()
4678 	if (status < 0)  in set_qam64()
4680 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);  in set_qam64()
4681 	if (status < 0)  in set_qam64()
4683 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);  in set_qam64()
4684 	if (status < 0)  in set_qam64()
4688 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);  in set_qam64()
4689 	if (status < 0)  in set_qam64()
4691 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);  in set_qam64()
4692 	if (status < 0)  in set_qam64()
4694 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);  in set_qam64()
4695 	if (status < 0)  in set_qam64()
4697 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);  in set_qam64()
4698 	if (status < 0)  in set_qam64()
4700 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);  in set_qam64()
4701 	if (status < 0)  in set_qam64()
4703 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam64()
4704 	if (status < 0)  in set_qam64()
4707 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam64()
4708 	if (status < 0)  in set_qam64()
4710 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam64()
4711 	if (status < 0)  in set_qam64()
4713 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam64()
4714 	if (status < 0)  in set_qam64()
4718 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam64()
4720 	if (status < 0)  in set_qam64()
4726 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam64()
4727 	if (status < 0)  in set_qam64()
4729 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam64()
4730 	if (status < 0)  in set_qam64()
4732 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam64()
4733 	if (status < 0)  in set_qam64()
4735 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam64()
4736 	if (status < 0)  in set_qam64()
4738 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam64()
4739 	if (status < 0)  in set_qam64()
4741 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam64()
4742 	if (status < 0)  in set_qam64()
4744 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam64()
4745 	if (status < 0)  in set_qam64()
4747 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam64()
4748 	if (status < 0)  in set_qam64()
4751 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam64()
4752 	if (status < 0)  in set_qam64()
4754 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);  in set_qam64()
4755 	if (status < 0)  in set_qam64()
4757 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);  in set_qam64()
4758 	if (status < 0)  in set_qam64()
4760 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam64()
4761 	if (status < 0)  in set_qam64()
4763 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);  in set_qam64()
4764 	if (status < 0)  in set_qam64()
4766 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam64()
4767 	if (status < 0)  in set_qam64()
4769 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam64()
4770 	if (status < 0)  in set_qam64()
4772 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam64()
4773 	if (status < 0)  in set_qam64()
4775 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);  in set_qam64()
4776 	if (status < 0)  in set_qam64()
4778 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam64()
4779 	if (status < 0)  in set_qam64()
4781 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam64()
4782 	if (status < 0)  in set_qam64()
4784 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam64()
4785 	if (status < 0)  in set_qam64()
4791 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);  in set_qam64()
4792 	if (status < 0)  in set_qam64()
4794 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam64()
4795 	if (status < 0)  in set_qam64()
4797 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam64()
4798 	if (status < 0)  in set_qam64()
4800 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);  in set_qam64()
4801 	if (status < 0)  in set_qam64()
4803 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);  in set_qam64()
4804 	if (status < 0)  in set_qam64()
4806 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);  in set_qam64()
4807 	if (status < 0)  in set_qam64()
4810 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam64()
4811 	if (status < 0)  in set_qam64()
4813 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam64()
4814 	if (status < 0)  in set_qam64()
4816 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);  in set_qam64()
4817 	if (status < 0)  in set_qam64()
4823 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);  in set_qam64()
4824 	if (status < 0)  in set_qam64()
4826 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);  in set_qam64()
4827 	if (status < 0)  in set_qam64()
4829 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);  in set_qam64()
4830 	if (status < 0)  in set_qam64()
4832 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);  in set_qam64()
4833 	if (status < 0)  in set_qam64()
4835 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);  in set_qam64()
4836 	if (status < 0)  in set_qam64()
4838 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);  in set_qam64()
4839 	if (status < 0)  in set_qam64()
4841 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);  in set_qam64()
4843 	if (status < 0)  in set_qam64()
4844 		pr_err("Error %d on %s\n", status, __func__);  in set_qam64()
4846 	return status;  in set_qam64()
4858 	int status = 0;  in set_qam128()  local
4863 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);  in set_qam128()
4864 	if (status < 0)  in set_qam128()
4866 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);  in set_qam128()
4867 	if (status < 0)  in set_qam128()
4869 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);  in set_qam128()
4870 	if (status < 0)  in set_qam128()
4872 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);  in set_qam128()
4873 	if (status < 0)  in set_qam128()
4875 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);  in set_qam128()
4876 	if (status < 0)  in set_qam128()
4878 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);  in set_qam128()
4879 	if (status < 0)  in set_qam128()
4883 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);  in set_qam128()
4884 	if (status < 0)  in set_qam128()
4886 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);  in set_qam128()
4887 	if (status < 0)  in set_qam128()
4889 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);  in set_qam128()
4890 	if (status < 0)  in set_qam128()
4892 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);  in set_qam128()
4893 	if (status < 0)  in set_qam128()
4895 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);  in set_qam128()
4896 	if (status < 0)  in set_qam128()
4898 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam128()
4899 	if (status < 0)  in set_qam128()
4902 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);  in set_qam128()
4903 	if (status < 0)  in set_qam128()
4905 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);  in set_qam128()
4906 	if (status < 0)  in set_qam128()
4908 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam128()
4909 	if (status < 0)  in set_qam128()
4915 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam128()
4917 	if (status < 0)  in set_qam128()
4923 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam128()
4924 	if (status < 0)  in set_qam128()
4926 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam128()
4927 	if (status < 0)  in set_qam128()
4929 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam128()
4930 	if (status < 0)  in set_qam128()
4932 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam128()
4933 	if (status < 0)  in set_qam128()
4935 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam128()
4936 	if (status < 0)  in set_qam128()
4938 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam128()
4939 	if (status < 0)  in set_qam128()
4941 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam128()
4942 	if (status < 0)  in set_qam128()
4944 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam128()
4945 	if (status < 0)  in set_qam128()
4948 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam128()
4949 	if (status < 0)  in set_qam128()
4951 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);  in set_qam128()
4952 	if (status < 0)  in set_qam128()
4954 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);  in set_qam128()
4955 	if (status < 0)  in set_qam128()
4957 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam128()
4958 	if (status < 0)  in set_qam128()
4960 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);  in set_qam128()
4961 	if (status < 0)  in set_qam128()
4963 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);  in set_qam128()
4964 	if (status < 0)  in set_qam128()
4966 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam128()
4967 	if (status < 0)  in set_qam128()
4969 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam128()
4970 	if (status < 0)  in set_qam128()
4972 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);  in set_qam128()
4973 	if (status < 0)  in set_qam128()
4975 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam128()
4976 	if (status < 0)  in set_qam128()
4978 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam128()
4979 	if (status < 0)  in set_qam128()
4981 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);  in set_qam128()
4982 	if (status < 0)  in set_qam128()
4988 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);  in set_qam128()
4989 	if (status < 0)  in set_qam128()
4991 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam128()
4992 	if (status < 0)  in set_qam128()
4994 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam128()
4995 	if (status < 0)  in set_qam128()
4997 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam128()
4998 	if (status < 0)  in set_qam128()
5000 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);  in set_qam128()
5001 	if (status < 0)  in set_qam128()
5003 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);  in set_qam128()
5004 	if (status < 0)  in set_qam128()
5007 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam128()
5008 	if (status < 0)  in set_qam128()
5010 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);  in set_qam128()
5011 	if (status < 0)  in set_qam128()
5014 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);  in set_qam128()
5015 	if (status < 0)  in set_qam128()
5020 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);  in set_qam128()
5021 	if (status < 0)  in set_qam128()
5023 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);  in set_qam128()
5024 	if (status < 0)  in set_qam128()
5026 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);  in set_qam128()
5027 	if (status < 0)  in set_qam128()
5029 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);  in set_qam128()
5030 	if (status < 0)  in set_qam128()
5032 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);  in set_qam128()
5033 	if (status < 0)  in set_qam128()
5035 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);  in set_qam128()
5036 	if (status < 0)  in set_qam128()
5038 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);  in set_qam128()
5040 	if (status < 0)  in set_qam128()
5041 		pr_err("Error %d on %s\n", status, __func__);  in set_qam128()
5043 	return status;  in set_qam128()
5055 	int status = 0;  in set_qam256()  local
5060 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);  in set_qam256()
5061 	if (status < 0)  in set_qam256()
5063 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);  in set_qam256()
5064 	if (status < 0)  in set_qam256()
5066 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);  in set_qam256()
5067 	if (status < 0)  in set_qam256()
5069 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);  in set_qam256()
5070 	if (status < 0)  in set_qam256()
5072 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);  in set_qam256()
5073 	if (status < 0)  in set_qam256()
5075 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);  in set_qam256()
5076 	if (status < 0)  in set_qam256()
5080 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);  in set_qam256()
5081 	if (status < 0)  in set_qam256()
5083 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);  in set_qam256()
5084 	if (status < 0)  in set_qam256()
5086 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);  in set_qam256()
5087 	if (status < 0)  in set_qam256()
5089 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);  in set_qam256()
5090 	if (status < 0)  in set_qam256()
5092 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);  in set_qam256()
5093 	if (status < 0)  in set_qam256()
5095 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam256()
5096 	if (status < 0)  in set_qam256()
5099 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam256()
5100 	if (status < 0)  in set_qam256()
5102 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam256()
5103 	if (status < 0)  in set_qam256()
5105 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam256()
5106 	if (status < 0)  in set_qam256()
5111 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam256()
5113 	if (status < 0)  in set_qam256()
5119 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam256()
5120 	if (status < 0)  in set_qam256()
5122 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam256()
5123 	if (status < 0)  in set_qam256()
5125 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam256()
5126 	if (status < 0)  in set_qam256()
5128 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam256()
5129 	if (status < 0)  in set_qam256()
5131 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam256()
5132 	if (status < 0)  in set_qam256()
5134 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam256()
5135 	if (status < 0)  in set_qam256()
5137 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam256()
5138 	if (status < 0)  in set_qam256()
5140 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam256()
5141 	if (status < 0)  in set_qam256()
5144 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam256()
5145 	if (status < 0)  in set_qam256()
5147 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);  in set_qam256()
5148 	if (status < 0)  in set_qam256()
5150 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);  in set_qam256()
5151 	if (status < 0)  in set_qam256()
5153 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam256()
5154 	if (status < 0)  in set_qam256()
5156 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);  in set_qam256()
5157 	if (status < 0)  in set_qam256()
5159 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);  in set_qam256()
5160 	if (status < 0)  in set_qam256()
5162 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam256()
5163 	if (status < 0)  in set_qam256()
5165 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam256()
5166 	if (status < 0)  in set_qam256()
5168 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);  in set_qam256()
5169 	if (status < 0)  in set_qam256()
5171 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam256()
5172 	if (status < 0)  in set_qam256()
5174 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam256()
5175 	if (status < 0)  in set_qam256()
5177 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam256()
5178 	if (status < 0)  in set_qam256()
5184 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);  in set_qam256()
5185 	if (status < 0)  in set_qam256()
5187 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam256()
5188 	if (status < 0)  in set_qam256()
5190 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam256()
5191 	if (status < 0)  in set_qam256()
5193 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam256()
5194 	if (status < 0)  in set_qam256()
5196 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);  in set_qam256()
5197 	if (status < 0)  in set_qam256()
5199 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);  in set_qam256()
5200 	if (status < 0)  in set_qam256()
5203 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam256()
5204 	if (status < 0)  in set_qam256()
5206 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam256()
5207 	if (status < 0)  in set_qam256()
5209 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);  in set_qam256()
5210 	if (status < 0)  in set_qam256()
5216 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);  in set_qam256()
5217 	if (status < 0)  in set_qam256()
5219 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);  in set_qam256()
5220 	if (status < 0)  in set_qam256()
5222 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);  in set_qam256()
5223 	if (status < 0)  in set_qam256()
5225 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);  in set_qam256()
5226 	if (status < 0)  in set_qam256()
5228 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);  in set_qam256()
5229 	if (status < 0)  in set_qam256()
5231 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);  in set_qam256()
5232 	if (status < 0)  in set_qam256()
5234 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);  in set_qam256()
5236 	if (status < 0)  in set_qam256()
5237 		pr_err("Error %d on %s\n", status, __func__);  in set_qam256()
5238 	return status;  in set_qam256()
5251 	int status;  in qam_reset_qam()  local
5256 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);  in qam_reset_qam()
5257 	if (status < 0)  in qam_reset_qam()
5260 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in qam_reset_qam()
5264 	if (status < 0)  in qam_reset_qam()
5265 		pr_err("Error %d on %s\n", status, __func__);  in qam_reset_qam()
5266 	return status;  in qam_reset_qam()
5284 	int status;  in qam_set_symbolrate()  local
5297 	status = write16(state, IQM_FD_RATESEL__A, ratesel);  in qam_set_symbolrate()
5298 	if (status < 0)  in qam_set_symbolrate()
5307 		status = -EINVAL;  in qam_set_symbolrate()
5313 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);  in qam_set_symbolrate()
5314 	if (status < 0)  in qam_set_symbolrate()
5323 		status = -EINVAL;  in qam_set_symbolrate()
5331 	status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);  in qam_set_symbolrate()
5334 	if (status < 0)  in qam_set_symbolrate()
5335 		pr_err("Error %d on %s\n", status, __func__);  in qam_set_symbolrate()
5336 	return status;  in qam_set_symbolrate()
5350 	int status;  in get_qam_lock_status()  local
5355 	status = scu_command(state,  in get_qam_lock_status()
5359 	if (status < 0)  in get_qam_lock_status()
5360 		pr_err("Error %d on %s\n", status, __func__);  in get_qam_lock_status()
5379 	return status;  in get_qam_lock_status()
5392 	int status;  in qam_demodulator_command()  local
5407 		status = scu_command(state,  in qam_demodulator_command()
5411 		if (status < 0)  in qam_demodulator_command()
5414 		status = scu_command(state,  in qam_demodulator_command()
5430 		status = scu_command(state,  in qam_demodulator_command()
5438 		status = -EINVAL;  in qam_demodulator_command()
5442 	if (status < 0)  in qam_demodulator_command()
5443 		pr_warn("Warning %d on %s\n", status, __func__);  in qam_demodulator_command()
5444 	return status;  in qam_demodulator_command()
5450 	int status;  in set_qam()  local
5461 	status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);  in set_qam()
5462 	if (status < 0)  in set_qam()
5464 	status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);  in set_qam()
5465 	if (status < 0)  in set_qam()
5467 	status = qam_reset_qam(state);  in set_qam()
5468 	if (status < 0)  in set_qam()
5476 	status = qam_set_symbolrate(state);  in set_qam()
5477 	if (status < 0)  in set_qam()
5499 		status = -EINVAL;  in set_qam()
5502 	if (status < 0)  in set_qam()
5510 		status = qam_demodulator_command(state, qam_demod_param_count);  in set_qam()
5517 		|| (!state->qam_demod_parameter_count && status < 0)) {  in set_qam()
5519 		status = qam_demodulator_command(state, qam_demod_param_count);  in set_qam()
5522 	if (status < 0) {  in set_qam()
5546 	status = set_frequency(channel, tuner_freq_offset));  in set_qam()
5547 	if (status < 0)  in set_qam()
5550 	status = set_frequency_shifter(state, intermediate_freqk_hz,  in set_qam()
5552 	if (status < 0)  in set_qam()
5556 	status = set_qam_measurement(state, state->m_constellation,  in set_qam()
5558 	if (status < 0)  in set_qam()
5562 	status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);  in set_qam()
5563 	if (status < 0)  in set_qam()
5565 	status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);  in set_qam()
5566 	if (status < 0)  in set_qam()
5570 	status = write16(state, QAM_LC_RATE_LIMIT__A, 3);  in set_qam()
5571 	if (status < 0)  in set_qam()
5573 	status = write16(state, QAM_LC_LPF_FACTORP__A, 4);  in set_qam()
5574 	if (status < 0)  in set_qam()
5576 	status = write16(state, QAM_LC_LPF_FACTORI__A, 4);  in set_qam()
5577 	if (status < 0)  in set_qam()
5579 	status = write16(state, QAM_LC_MODE__A, 7);  in set_qam()
5580 	if (status < 0)  in set_qam()
5583 	status = write16(state, QAM_LC_QUAL_TAB0__A, 1);  in set_qam()
5584 	if (status < 0)  in set_qam()
5586 	status = write16(state, QAM_LC_QUAL_TAB1__A, 1);  in set_qam()
5587 	if (status < 0)  in set_qam()
5589 	status = write16(state, QAM_LC_QUAL_TAB2__A, 1);  in set_qam()
5590 	if (status < 0)  in set_qam()
5592 	status = write16(state, QAM_LC_QUAL_TAB3__A, 1);  in set_qam()
5593 	if (status < 0)  in set_qam()
5595 	status = write16(state, QAM_LC_QUAL_TAB4__A, 2);  in set_qam()
5596 	if (status < 0)  in set_qam()
5598 	status = write16(state, QAM_LC_QUAL_TAB5__A, 2);  in set_qam()
5599 	if (status < 0)  in set_qam()
5601 	status = write16(state, QAM_LC_QUAL_TAB6__A, 2);  in set_qam()
5602 	if (status < 0)  in set_qam()
5604 	status = write16(state, QAM_LC_QUAL_TAB8__A, 2);  in set_qam()
5605 	if (status < 0)  in set_qam()
5607 	status = write16(state, QAM_LC_QUAL_TAB9__A, 2);  in set_qam()
5608 	if (status < 0)  in set_qam()
5610 	status = write16(state, QAM_LC_QUAL_TAB10__A, 2);  in set_qam()
5611 	if (status < 0)  in set_qam()
5613 	status = write16(state, QAM_LC_QUAL_TAB12__A, 2);  in set_qam()
5614 	if (status < 0)  in set_qam()
5616 	status = write16(state, QAM_LC_QUAL_TAB15__A, 3);  in set_qam()
5617 	if (status < 0)  in set_qam()
5619 	status = write16(state, QAM_LC_QUAL_TAB16__A, 3);  in set_qam()
5620 	if (status < 0)  in set_qam()
5622 	status = write16(state, QAM_LC_QUAL_TAB20__A, 4);  in set_qam()
5623 	if (status < 0)  in set_qam()
5625 	status = write16(state, QAM_LC_QUAL_TAB25__A, 4);  in set_qam()
5626 	if (status < 0)  in set_qam()
5630 	status = write16(state, QAM_SY_SP_INV__A,  in set_qam()
5632 	if (status < 0)  in set_qam()
5636 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_qam()
5637 	if (status < 0)  in set_qam()
5643 		status = set_qam16(state);  in set_qam()
5646 		status = set_qam32(state);  in set_qam()
5650 		status = set_qam64(state);  in set_qam()
5653 		status = set_qam128(state);  in set_qam()
5656 		status = set_qam256(state);  in set_qam()
5659 		status = -EINVAL;  in set_qam()
5662 	if (status < 0)  in set_qam()
5666 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_qam()
5667 	if (status < 0)  in set_qam()
5673 	status = mpegts_dto_setup(state, state->m_operation_mode);  in set_qam()
5674 	if (status < 0)  in set_qam()
5678 	status = mpegts_start(state);  in set_qam()
5679 	if (status < 0)  in set_qam()
5681 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);  in set_qam()
5682 	if (status < 0)  in set_qam()
5684 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);  in set_qam()
5685 	if (status < 0)  in set_qam()
5687 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);  in set_qam()
5688 	if (status < 0)  in set_qam()
5692 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in set_qam()
5695 	if (status < 0)  in set_qam()
5702 	if (status < 0)  in set_qam()
5703 		pr_err("Error %d on %s\n", status, __func__);  in set_qam()
5704 	return status;  in set_qam()
5710 	int status;  in set_qam_standard()  local
5723 	status = power_up_qam(state);  in set_qam_standard()
5724 	if (status < 0)  in set_qam_standard()
5727 	status = qam_reset_qam(state);  in set_qam_standard()
5728 	if (status < 0)  in set_qam_standard()
5733 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in set_qam_standard()
5734 	if (status < 0)  in set_qam_standard()
5736 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);  in set_qam_standard()
5737 	if (status < 0)  in set_qam_standard()
5744 		status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,  in set_qam_standard()
5749 		status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,  in set_qam_standard()
5753 		if (status < 0)  in set_qam_standard()
5755 		status = bl_direct_cmd(state,  in set_qam_standard()
5762 		status = -EINVAL;  in set_qam_standard()
5764 	if (status < 0)  in set_qam_standard()
5767 	status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);  in set_qam_standard()
5768 	if (status < 0)  in set_qam_standard()
5770 	status = write16(state, IQM_CF_SYMMETRIC__A, 0);  in set_qam_standard()
5771 	if (status < 0)  in set_qam_standard()
5773 	status = write16(state, IQM_CF_MIDTAP__A,  in set_qam_standard()
5775 	if (status < 0)  in set_qam_standard()
5778 	status = write16(state, IQM_RC_STRETCH__A, 21);  in set_qam_standard()
5779 	if (status < 0)  in set_qam_standard()
5781 	status = write16(state, IQM_AF_CLP_LEN__A, 0);  in set_qam_standard()
5782 	if (status < 0)  in set_qam_standard()
5784 	status = write16(state, IQM_AF_CLP_TH__A, 448);  in set_qam_standard()
5785 	if (status < 0)  in set_qam_standard()
5787 	status = write16(state, IQM_AF_SNS_LEN__A, 0);  in set_qam_standard()
5788 	if (status < 0)  in set_qam_standard()
5790 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);  in set_qam_standard()
5791 	if (status < 0)  in set_qam_standard()
5794 	status = write16(state, IQM_FS_ADJ_SEL__A, 1);  in set_qam_standard()
5795 	if (status < 0)  in set_qam_standard()
5797 	status = write16(state, IQM_RC_ADJ_SEL__A, 1);  in set_qam_standard()
5798 	if (status < 0)  in set_qam_standard()
5800 	status = write16(state, IQM_CF_ADJ_SEL__A, 1);  in set_qam_standard()
5801 	if (status < 0)  in set_qam_standard()
5803 	status = write16(state, IQM_AF_UPD_SEL__A, 0);  in set_qam_standard()
5804 	if (status < 0)  in set_qam_standard()
5808 	status = write16(state, IQM_CF_CLP_VAL__A, 500);  in set_qam_standard()
5809 	if (status < 0)  in set_qam_standard()
5811 	status = write16(state, IQM_CF_DATATH__A, 1000);  in set_qam_standard()
5812 	if (status < 0)  in set_qam_standard()
5814 	status = write16(state, IQM_CF_BYPASSDET__A, 1);  in set_qam_standard()
5815 	if (status < 0)  in set_qam_standard()
5817 	status = write16(state, IQM_CF_DET_LCT__A, 0);  in set_qam_standard()
5818 	if (status < 0)  in set_qam_standard()
5820 	status = write16(state, IQM_CF_WND_LEN__A, 1);  in set_qam_standard()
5821 	if (status < 0)  in set_qam_standard()
5823 	status = write16(state, IQM_CF_PKDTH__A, 1);  in set_qam_standard()
5824 	if (status < 0)  in set_qam_standard()
5826 	status = write16(state, IQM_AF_INC_BYPASS__A, 1);  in set_qam_standard()
5827 	if (status < 0)  in set_qam_standard()
5831 	status = set_iqm_af(state, true);  in set_qam_standard()
5832 	if (status < 0)  in set_qam_standard()
5834 	status = write16(state, IQM_AF_START_LOCK__A, 0x01);  in set_qam_standard()
5835 	if (status < 0)  in set_qam_standard()
5839 	status = adc_synchronization(state);  in set_qam_standard()
5840 	if (status < 0)  in set_qam_standard()
5844 	status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);  in set_qam_standard()
5845 	if (status < 0)  in set_qam_standard()
5849 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_qam_standard()
5850 	if (status < 0)  in set_qam_standard()
5856 	status = init_agc(state, true);  in set_qam_standard()
5857 	if (status < 0)  in set_qam_standard()
5859 	status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));  in set_qam_standard()
5860 	if (status < 0)  in set_qam_standard()
5864 	status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);  in set_qam_standard()
5865 	if (status < 0)  in set_qam_standard()
5867 	status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);  in set_qam_standard()
5868 	if (status < 0)  in set_qam_standard()
5872 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_qam_standard()
5874 	if (status < 0)  in set_qam_standard()
5875 		pr_err("Error %d on %s\n", status, __func__);  in set_qam_standard()
5876 	return status;  in set_qam_standard()
5881 	int status;  in write_gpio()  local
5886 	status = write16(state, SCU_RAM_GPIO__A,  in write_gpio()
5888 	if (status < 0)  in write_gpio()
5892 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in write_gpio()
5893 	if (status < 0)  in write_gpio()
5899 			status = write16(state, SIO_PDR_SMA_TX_CFG__A,  in write_gpio()
5901 			if (status < 0)  in write_gpio()
5905 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5906 			if (status < 0)  in write_gpio()
5913 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5914 			if (status < 0)  in write_gpio()
5919 			status = write16(state, SIO_PDR_SMA_RX_CFG__A,  in write_gpio()
5921 			if (status < 0)  in write_gpio()
5925 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5926 			if (status < 0)  in write_gpio()
5933 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5934 			if (status < 0)  in write_gpio()
5939 			status = write16(state, SIO_PDR_GPIO_CFG__A,  in write_gpio()
5941 			if (status < 0)  in write_gpio()
5945 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5946 			if (status < 0)  in write_gpio()
5953 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5954 			if (status < 0)  in write_gpio()
5959 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in write_gpio()
5961 	if (status < 0)  in write_gpio()
5962 		pr_err("Error %d on %s\n", status, __func__);  in write_gpio()
5963 	return status;  in write_gpio()
5968 	int status = 0;  in switch_antenna_to_qam()  local
5984 		status = write_gpio(state);  in switch_antenna_to_qam()
5986 	if (status < 0)  in switch_antenna_to_qam()
5987 		pr_err("Error %d on %s\n", status, __func__);  in switch_antenna_to_qam()
5988 	return status;  in switch_antenna_to_qam()
5993 	int status = 0;  in switch_antenna_to_dvbt()  local
6009 		status = write_gpio(state);  in switch_antenna_to_dvbt()
6011 	if (status < 0)  in switch_antenna_to_dvbt()
6012 		pr_err("Error %d on %s\n", status, __func__);  in switch_antenna_to_dvbt()
6013 	return status;  in switch_antenna_to_dvbt()
6025 	int status;  in power_down_device()  local
6030 		status = ConfigureI2CBridge(state, true);  in power_down_device()
6031 		if (status < 0)  in power_down_device()
6035 	status = dvbt_enable_ofdm_token_ring(state, false);  in power_down_device()
6036 	if (status < 0)  in power_down_device()
6039 	status = write16(state, SIO_CC_PWD_MODE__A,  in power_down_device()
6041 	if (status < 0)  in power_down_device()
6043 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in power_down_device()
6044 	if (status < 0)  in power_down_device()
6047 	status = hi_cfg_command(state);  in power_down_device()
6049 	if (status < 0)  in power_down_device()
6050 		pr_err("Error %d on %s\n", status, __func__);  in power_down_device()
6052 	return status;  in power_down_device()
6057 	int status = 0, n = 0;  in init_drxk()  local
6064 		status = power_up_device(state);  in init_drxk()
6065 		if (status < 0)  in init_drxk()
6067 		status = drxx_open(state);  in init_drxk()
6068 		if (status < 0)  in init_drxk()
6071 		status = write16(state, SIO_CC_SOFT_RST__A,  in init_drxk()
6075 		if (status < 0)  in init_drxk()
6077 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in init_drxk()
6078 		if (status < 0)  in init_drxk()
6086 		status = get_device_capabilities(state);  in init_drxk()
6087 		if (status < 0)  in init_drxk()
6107 		status = init_hi(state);  in init_drxk()
6108 		if (status < 0)  in init_drxk()
6116 			status = write16(state, SCU_RAM_GPIO__A,  in init_drxk()
6118 			if (status < 0)  in init_drxk()
6123 		status = mpegts_disable(state);  in init_drxk()
6124 		if (status < 0)  in init_drxk()
6128 		status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);  in init_drxk()
6129 		if (status < 0)  in init_drxk()
6131 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);  in init_drxk()
6132 		if (status < 0)  in init_drxk()
6136 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,  in init_drxk()
6138 		if (status < 0)  in init_drxk()
6142 		status = write16(state, SIO_BL_COMM_EXEC__A,  in init_drxk()
6144 		if (status < 0)  in init_drxk()
6146 		status = bl_chain_cmd(state, 0, 6, 100);  in init_drxk()
6147 		if (status < 0)  in init_drxk()
6151 			status = download_microcode(state, state->fw->data,  in init_drxk()
6153 			if (status < 0)  in init_drxk()
6158 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,  in init_drxk()
6160 		if (status < 0)  in init_drxk()
6164 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in init_drxk()
6165 		if (status < 0)  in init_drxk()
6167 		status = drxx_open(state);  in init_drxk()
6168 		if (status < 0)  in init_drxk()
6174 		status = ctrl_power_mode(state, &power_mode);  in init_drxk()
6175 		if (status < 0)  in init_drxk()
6189 		status = write16(state, SCU_RAM_DRIVER_VER_HI__A,  in init_drxk()
6191 		if (status < 0)  in init_drxk()
6198 		status = write16(state, SCU_RAM_DRIVER_VER_LO__A,  in init_drxk()
6200 		if (status < 0)  in init_drxk()
6218 		status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);  in init_drxk()
6219 		if (status < 0)  in init_drxk()
6224 		status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);  in init_drxk()
6225 		if (status < 0)  in init_drxk()
6228 		status = mpegts_dto_init(state);  in init_drxk()
6229 		if (status < 0)  in init_drxk()
6231 		status = mpegts_stop(state);  in init_drxk()
6232 		if (status < 0)  in init_drxk()
6234 		status = mpegts_configure_polarity(state);  in init_drxk()
6235 		if (status < 0)  in init_drxk()
6237 		status = mpegts_configure_pins(state, state->m_enable_mpeg_output);  in init_drxk()
6238 		if (status < 0)  in init_drxk()
6241 		status = write_gpio(state);  in init_drxk()
6242 		if (status < 0)  in init_drxk()
6248 			status = power_down_device(state);  in init_drxk()
6249 			if (status < 0)  in init_drxk()
6271 	if (status < 0) {  in init_drxk()
6274 		pr_err("Error %d on %s\n", status, __func__);  in init_drxk()
6277 	return status;  in init_drxk()
6420 	int status;  in get_strength()  local
6446 		status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);  in get_strength()
6447 		if (status < 0)  in get_strength()
6448 			return status;  in get_strength()
6451 		status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);  in get_strength()
6452 		if (status < 0)  in get_strength()
6453 			return status;  in get_strength()
6479 		status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,  in get_strength()
6481 		if (status < 0)  in get_strength()
6482 			return status;  in get_strength()
6484 		status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,  in get_strength()
6486 		if (status < 0)  in get_strength()
6487 			return status;  in get_strength()
6523 	int status;  in drxk_get_stats()  local
6586 	status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16);  in drxk_get_stats()
6587 	if (status < 0)  in drxk_get_stats()
6591 	status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , &reg16);  in drxk_get_stats()
6592 	if (status < 0)  in drxk_get_stats()
6597 	status = read16(state, FEC_RS_NR_BIT_ERRORS__A, &reg16);  in drxk_get_stats()
6598 	if (status < 0)  in drxk_get_stats()
6602 	status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, &reg16);  in drxk_get_stats()
6603 	if (status < 0)  in drxk_get_stats()
6607 	status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, &reg16);  in drxk_get_stats()
6608 	if (status < 0)  in drxk_get_stats()
6612 	status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &reg16);  in drxk_get_stats()
6613 	if (status < 0)  in drxk_get_stats()
6639 	return status;  in drxk_get_stats()
6643 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)  in drxk_read_status()  argument
6654 	*status = state->fe_status;  in drxk_read_status()
6779 	int status;  in drxk_attach()  local
6836 		status = request_firmware(&fw, state->microcode_name,  in drxk_attach()
6838 		if (status < 0)  in drxk_attach()