Lines Matching refs:REG_AWB_AUTO
26 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
33 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
40 REG_AE_ALL, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
47 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
54 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
61 REG_AE_CENTER, REG_AE_INDEX_10_POS, REG_AWB_AUTO, 0,
84 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
91 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
98 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
105 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
112 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
119 REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
290 { V4L2_WHITE_BALANCE_AUTO, REG_AWB_AUTO }, in m5mols_set_white_balance()
305 ret = m5mols_write(sd, AWB_MODE, awb ? REG_AWB_AUTO : in m5mols_set_white_balance()