102 	tw_writeb(TW68_ACNTL, 0x80);	/* 218	soft reset */  in tw68_hw_init1()
105 	tw_writeb(TW68_INFORM, 0x40);	/* 208	mux0, 27mhz xtal */  in tw68_hw_init1()
106 	tw_writeb(TW68_OPFORM, 0x04);	/* 20C	analog line-lock */  in tw68_hw_init1()
107 	tw_writeb(TW68_HSYNC, 0);	/* 210	color-killer high sens */  in tw68_hw_init1()
108 	tw_writeb(TW68_ACNTL, 0x42);	/* 218	int vref #2, chroma adc off */  in tw68_hw_init1()
110 	tw_writeb(TW68_CROP_HI, 0x02);	/* 21C	Hactive m.s. bits */  in tw68_hw_init1()
111 	tw_writeb(TW68_VDELAY_LO, 0x12);/* 220	Mfg specified reset value */  in tw68_hw_init1()
112 	tw_writeb(TW68_VACTIVE_LO, 0xf0);  in tw68_hw_init1()
113 	tw_writeb(TW68_HDELAY_LO, 0x0f);  in tw68_hw_init1()
114 	tw_writeb(TW68_HACTIVE_LO, 0xd0);  in tw68_hw_init1()
116 	tw_writeb(TW68_CNTRL1, 0xcd);	/* 230	Wide Chroma BPF B/W  in tw68_hw_init1()
120 	tw_writeb(TW68_VSCALE_LO, 0);	/* 234 */  in tw68_hw_init1()
121 	tw_writeb(TW68_SCALE_HI, 0x11);	/* 238 */  in tw68_hw_init1()
122 	tw_writeb(TW68_HSCALE_LO, 0);	/* 23c */  in tw68_hw_init1()
123 	tw_writeb(TW68_BRIGHT, 0);	/* 240 */  in tw68_hw_init1()
124 	tw_writeb(TW68_CONTRAST, 0x5c);	/* 244 */  in tw68_hw_init1()
125 	tw_writeb(TW68_SHARPNESS, 0x51);/* 248 */  in tw68_hw_init1()
126 	tw_writeb(TW68_SAT_U, 0x80);	/* 24C */  in tw68_hw_init1()
127 	tw_writeb(TW68_SAT_V, 0x80);	/* 250 */  in tw68_hw_init1()
128 	tw_writeb(TW68_HUE, 0x00);	/* 254 */  in tw68_hw_init1()
131 	tw_writeb(TW68_SHARP2, 0x53);	/* 258	Mfg specified reset val */  in tw68_hw_init1()
132 	tw_writeb(TW68_VSHARP, 0x80);	/* 25C	Sharpness Coring val 8 */  in tw68_hw_init1()
133 	tw_writeb(TW68_CORING, 0x44);	/* 260	CTI and Vert Peak coring */  in tw68_hw_init1()
134 	tw_writeb(TW68_CNTRL2, 0x00);	/* 268	No power saving enabled */  in tw68_hw_init1()
135 	tw_writeb(TW68_SDT, 0x07);	/* 270	Enable shadow reg, auto-det */  in tw68_hw_init1()
136 	tw_writeb(TW68_SDTR, 0x7f);	/* 274	All stds recog, don't start */  in tw68_hw_init1()
137 	tw_writeb(TW68_CLMPG, 0x50);	/* 280	Clamp end at 40 sys clocks */  in tw68_hw_init1()
138 	tw_writeb(TW68_IAGC, 0x22);	/* 284	Mfg specified reset val */  in tw68_hw_init1()
139 	tw_writeb(TW68_AGCGAIN, 0xf0);	/* 288	AGC gain when loop disabled */  in tw68_hw_init1()
140 	tw_writeb(TW68_PEAKWT, 0xd8);	/* 28C	White peak threshold */  in tw68_hw_init1()
141 	tw_writeb(TW68_CLMPL, 0x3c);	/* 290	Y channel clamp level */  in tw68_hw_init1()
143 	tw_writeb(TW68_SYNCT, 0x30);	/* 294	Sync amplitude */  in tw68_hw_init1()
144 	tw_writeb(TW68_MISSCNT, 0x44);	/* 298	Horiz sync, VCR detect sens */  in tw68_hw_init1()
145 	tw_writeb(TW68_PCLAMP, 0x28);	/* 29C	Clamp pos from PLL sync */  in tw68_hw_init1()
147 	tw_writeb(TW68_VCNTL1, 0x04);	/* 2A0 */  in tw68_hw_init1()
148 	tw_writeb(TW68_VCNTL2, 0);	/* 2A4 */  in tw68_hw_init1()
149 	tw_writeb(TW68_CKILL, 0x68);	/* 2A8	Mfg specified reset val */  in tw68_hw_init1()
150 	tw_writeb(TW68_COMB, 0x44);	/* 2AC	Mfg specified reset val */  in tw68_hw_init1()
151 	tw_writeb(TW68_LDLY, 0x30);	/* 2B0	Max positive luma delay */  in tw68_hw_init1()
152 	tw_writeb(TW68_MISC1, 0x14);	/* 2B4	Mfg specified reset val */  in tw68_hw_init1()
153 	tw_writeb(TW68_LOOP, 0xa5);	/* 2B8	Mfg specified reset val */  in tw68_hw_init1()
154 	tw_writeb(TW68_MISC2, 0xe0);	/* 2BC	Enable colour killer */  in tw68_hw_init1()
155 	tw_writeb(TW68_MVSN, 0);	/* 2C0 */  in tw68_hw_init1()
156 	tw_writeb(TW68_CLMD, 0x05);	/* 2CC	slice level auto, clamp med. */  in tw68_hw_init1()
157 	tw_writeb(TW68_IDCNTL, 0);	/* 2D0	Writing zero to this register  in tw68_hw_init1()
164 	tw_writeb(TW68_CLCNTL1, 0);	/* 2D4 */  in tw68_hw_init1()