Lines Matching refs:BIT
63 #define ALX_UE_SVRT_FCPROTERR BIT(13)
64 #define ALX_UE_SVRT_DLPROTERR BIT(4)
68 #define ALX_EFLD_F_EXIST BIT(10)
69 #define ALX_EFLD_E_EXIST BIT(9)
70 #define ALX_EFLD_STAT BIT(5)
71 #define ALX_EFLD_START BIT(0)
75 #define ALX_SLD_STAT BIT(12)
76 #define ALX_SLD_START BIT(11)
80 #define ALX_PDLL_TRNS1_D3PLLOFF_EN BIT(11)
83 #define ALX_PMCTRL_HOTRST_WTEN BIT(31)
85 #define ALX_PMCTRL_ASPM_FCEN BIT(30)
86 #define ALX_PMCTRL_SADLY_EN BIT(29)
94 #define ALX_PMCTRL_TXL1_AFTER_L0S BIT(19)
98 #define ALX_PMCTRL_RCVR_WT_1US BIT(15)
100 #define ALX_PMCTRL_L1_CLKSW_EN BIT(13)
101 #define ALX_PMCTRL_L0S_EN BIT(12)
102 #define ALX_PMCTRL_RXL1_AFTER_L0S BIT(11)
103 #define ALX_PMCTRL_L1_BUFSRX_EN BIT(7)
105 #define ALX_PMCTRL_L1_SRDSRX_PWD BIT(6)
106 #define ALX_PMCTRL_L1_SRDSPLL_EN BIT(5)
107 #define ALX_PMCTRL_L1_SRDS_EN BIT(4)
108 #define ALX_PMCTRL_L1_EN BIT(3)
116 #define ALX_MASTER_PCLKSEL_SRDS BIT(12)
118 #define ALX_MASTER_IRQMOD2_EN BIT(11)
120 #define ALX_MASTER_IRQMOD1_EN BIT(10)
121 #define ALX_MASTER_SYSALVTIMER_EN BIT(7)
122 #define ALX_MASTER_OOB_DIS BIT(6)
124 #define ALX_MASTER_WAKEN_25M BIT(5)
126 #define ALX_MASTER_DMA_MAC_RST BIT(0)
134 #define ALX_PHY_CTRL_100AB_EN BIT(17)
136 #define ALX_PHY_CTRL_POWER_DOWN BIT(14)
138 #define ALX_PHY_CTRL_PLL_ON BIT(13)
139 #define ALX_PHY_CTRL_RST_ANALOG BIT(12)
140 #define ALX_PHY_CTRL_HIB_PULSE BIT(11)
141 #define ALX_PHY_CTRL_HIB_EN BIT(10)
142 #define ALX_PHY_CTRL_IDDQ BIT(7)
143 #define ALX_PHY_CTRL_GATE_25M BIT(5)
144 #define ALX_PHY_CTRL_LED_MODE BIT(2)
146 #define ALX_PHY_CTRL_DSPRST_OUT BIT(0)
153 #define ALX_MAC_STS_TXQ_BUSY BIT(3)
154 #define ALX_MAC_STS_RXQ_BUSY BIT(2)
155 #define ALX_MAC_STS_TXMAC_BUSY BIT(1)
156 #define ALX_MAC_STS_RXMAC_BUSY BIT(0)
163 #define ALX_MDIO_MODE_EXT BIT(30)
164 #define ALX_MDIO_BUSY BIT(27)
169 #define ALX_MDIO_START BIT(23)
170 #define ALX_MDIO_SPRES_PRMBL BIT(22)
172 #define ALX_MDIO_OP_READ BIT(21)
186 #define ALX_SERDES_PHYCLK_SLWDWN BIT(18)
187 #define ALX_SERDES_MACCLK_SLWDWN BIT(17)
190 #define ALX_LPI_CTRL_EN BIT(0)
196 #define L1F_HRTBT_EXT_CTRL_SWOI_STARTUP_PKT_EN BIT(23)
197 #define L1F_HRTBT_EXT_CTRL_IOAC_2_FRAGMENTED BIT(22)
198 #define L1F_HRTBT_EXT_CTRL_IOAC_1_FRAGMENTED BIT(21)
199 #define L1F_HRTBT_EXT_CTRL_IOAC_1_KEEPALIVE_EN BIT(20)
200 #define L1F_HRTBT_EXT_CTRL_IOAC_1_HAS_VLAN BIT(19)
201 #define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_8023 BIT(18)
202 #define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_IPV6 BIT(17)
203 #define L1F_HRTBT_EXT_CTRL_IOAC_2_KEEPALIVE_EN BIT(16)
204 #define L1F_HRTBT_EXT_CTRL_IOAC_2_HAS_VLAN BIT(15)
205 #define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_8023 BIT(14)
206 #define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_IPV6 BIT(13)
207 #define ALX_HRTBT_EXT_CTRL_NS_EN BIT(12)
210 #define ALX_HRTBT_EXT_CTRL_IS_8023 BIT(3)
211 #define ALX_HRTBT_EXT_CTRL_IS_IPV6 BIT(2)
212 #define ALX_HRTBT_EXT_CTRL_WAKEUP_EN BIT(1)
213 #define ALX_HRTBT_EXT_CTRL_ARP_EN BIT(0)
224 #define ALX_SWOI_ORIG_ACK_NAK_EN BIT(20)
252 #define ALX_MAC_CTRL_FAST_PAUSE BIT(31)
253 #define ALX_MAC_CTRL_WOLSPED_SWEN BIT(30)
255 #define ALX_MAC_CTRL_MHASH_ALG_HI5B BIT(29)
256 #define ALX_MAC_CTRL_BRD_EN BIT(26)
257 #define ALX_MAC_CTRL_MULTIALL_EN BIT(25)
262 #define ALX_MAC_CTRL_PROMISC_EN BIT(15)
263 #define ALX_MAC_CTRL_VLANSTRIP BIT(14)
266 #define ALX_MAC_CTRL_PCRCE BIT(7)
267 #define ALX_MAC_CTRL_CRCE BIT(6)
268 #define ALX_MAC_CTRL_FULLD BIT(5)
269 #define ALX_MAC_CTRL_RXFC_EN BIT(3)
270 #define ALX_MAC_CTRL_TXFC_EN BIT(2)
271 #define ALX_MAC_CTRL_RX_EN BIT(1)
272 #define ALX_MAC_CTRL_TX_EN BIT(0)
290 #define ALX_SRAM_LOAD_PTR BIT(0)
327 #define ALX_TXQ0_LSO_8023_EN BIT(7)
328 #define ALX_TXQ0_MODE_ENHANCE BIT(6)
329 #define ALX_TXQ0_EN BIT(5)
330 #define ALX_TXQ0_SUPT_IPOPT BIT(4)
337 #define ALX_TXQ1_ERRLGPKT_DROP_EN BIT(11)
341 #define ALX_RXQ0_EN BIT(31)
342 #define ALX_RXQ0_RSS_HASH_EN BIT(29)
354 #define ALX_RXQ0_IPV6_PARSE_EN BIT(7)
357 #define ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN BIT(5)
358 #define ALX_RXQ0_RSS_HSTYP_IPV6_EN BIT(4)
359 #define ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN BIT(3)
360 #define ALX_RXQ0_RSS_HSTYP_IPV4_EN BIT(2)
390 #define ALX_DMA_RREQ_PRI_DATA BIT(10)
398 #define ALX_WOL0_PME_LINK BIT(5)
399 #define ALX_WOL0_LINK_EN BIT(4)
400 #define ALX_WOL0_PME_MAGIC_EN BIT(3)
401 #define ALX_WOL0_MAGIC_EN BIT(2)
464 #define ALX_ISR_DIS BIT(31)
465 #define ALX_ISR_RX_Q7 BIT(30)
466 #define ALX_ISR_RX_Q6 BIT(29)
467 #define ALX_ISR_RX_Q5 BIT(28)
468 #define ALX_ISR_RX_Q4 BIT(27)
469 #define ALX_ISR_PCIE_LNKDOWN BIT(26)
470 #define ALX_ISR_RX_Q3 BIT(19)
471 #define ALX_ISR_RX_Q2 BIT(18)
472 #define ALX_ISR_RX_Q1 BIT(17)
473 #define ALX_ISR_RX_Q0 BIT(16)
474 #define ALX_ISR_TX_Q0 BIT(15)
475 #define ALX_ISR_PHY BIT(12)
476 #define ALX_ISR_DMAW BIT(10)
477 #define ALX_ISR_DMAR BIT(9)
478 #define ALX_ISR_TXF_UR BIT(8)
479 #define ALX_ISR_TX_Q3 BIT(7)
480 #define ALX_ISR_TX_Q2 BIT(6)
481 #define ALX_ISR_TX_Q1 BIT(5)
482 #define ALX_ISR_RFD_UR BIT(4)
483 #define ALX_ISR_RXF_OV BIT(3)
484 #define ALX_ISR_MANU BIT(2)
485 #define ALX_ISR_TIMER BIT(1)
486 #define ALX_ISR_SMB BIT(0)
502 #define ALX_CLK_GATE_RXMAC BIT(5)
503 #define ALX_CLK_GATE_TXMAC BIT(4)
504 #define ALX_CLK_GATE_RXQ BIT(3)
505 #define ALX_CLK_GATE_TXQ BIT(2)
506 #define ALX_CLK_GATE_DMAR BIT(1)
507 #define ALX_CLK_GATE_DMAW BIT(0)
517 #define ALX_DRV_PHY_AUTO BIT(28)
518 #define ALX_DRV_PHY_1000 BIT(27)
519 #define ALX_DRV_PHY_100 BIT(26)
520 #define ALX_DRV_PHY_10 BIT(25)
521 #define ALX_DRV_PHY_DUPLEX BIT(24)
523 #define ALX_DRV_PHY_PAUSE BIT(23)
534 #define ALX_WOL_CTRL2_DATA_STORE BIT(3)
535 #define ALX_WOL_CTRL2_PTRN_EVT BIT(2)
536 #define ALX_WOL_CTRL2_PME_PTRN_EN BIT(1)
537 #define ALX_WOL_CTRL2_PTRN_EN BIT(0)
544 #define ALX_WOL_CTRL4_PT15_MATCH BIT(31)
545 #define ALX_WOL_CTRL4_PT14_MATCH BIT(30)
546 #define ALX_WOL_CTRL4_PT13_MATCH BIT(29)
547 #define ALX_WOL_CTRL4_PT12_MATCH BIT(28)
548 #define ALX_WOL_CTRL4_PT11_MATCH BIT(27)
549 #define ALX_WOL_CTRL4_PT10_MATCH BIT(26)
550 #define ALX_WOL_CTRL4_PT9_MATCH BIT(25)
551 #define ALX_WOL_CTRL4_PT8_MATCH BIT(24)
552 #define ALX_WOL_CTRL4_PT7_MATCH BIT(23)
553 #define ALX_WOL_CTRL4_PT6_MATCH BIT(22)
554 #define ALX_WOL_CTRL4_PT5_MATCH BIT(21)
555 #define ALX_WOL_CTRL4_PT4_MATCH BIT(20)
556 #define ALX_WOL_CTRL4_PT3_MATCH BIT(19)
557 #define ALX_WOL_CTRL4_PT2_MATCH BIT(18)
558 #define ALX_WOL_CTRL4_PT1_MATCH BIT(17)
559 #define ALX_WOL_CTRL4_PT0_MATCH BIT(16)
560 #define ALX_WOL_CTRL4_PT15_EN BIT(15)
561 #define ALX_WOL_CTRL4_PT14_EN BIT(14)
562 #define ALX_WOL_CTRL4_PT13_EN BIT(13)
563 #define ALX_WOL_CTRL4_PT12_EN BIT(12)
564 #define ALX_WOL_CTRL4_PT11_EN BIT(11)
565 #define ALX_WOL_CTRL4_PT10_EN BIT(10)
566 #define ALX_WOL_CTRL4_PT9_EN BIT(9)
567 #define ALX_WOL_CTRL4_PT8_EN BIT(8)
568 #define ALX_WOL_CTRL4_PT7_EN BIT(7)
569 #define ALX_WOL_CTRL4_PT6_EN BIT(6)
570 #define ALX_WOL_CTRL4_PT5_EN BIT(5)
571 #define ALX_WOL_CTRL4_PT4_EN BIT(4)
572 #define ALX_WOL_CTRL4_PT3_EN BIT(3)
573 #define ALX_WOL_CTRL4_PT2_EN BIT(2)
574 #define ALX_WOL_CTRL4_PT1_EN BIT(1)
575 #define ALX_WOL_CTRL4_PT0_EN BIT(0)
642 #define ALX_ACER_MAGIC_EN BIT(31)
643 #define ALX_ACER_MAGIC_PME_EN BIT(30)
644 #define ALX_ACER_MAGIC_MATCH BIT(29)
645 #define ALX_ACER_MAGIC_FF_CHECK BIT(10)
652 #define ALX_ACER_TIMER_EN BIT(31)
653 #define ALX_ACER_TIMER_PME_EN BIT(30)
654 #define ALX_ACER_TIMER_MATCH BIT(29)
693 #define ALX_MSI_MASK_SEL_LINE BIT(16)
714 #define ALX_HQTPD_BURST_EN BIT(31)
726 #define ALX_MISC_ISO_EN BIT(12)
727 #define ALX_MISC_INTNLOSC_OPEN BIT(3)
730 #define ALX_MSIC2_CALB_START BIT(0)
734 #define ALX_MISC3_25M_BY_SW BIT(1)
736 #define ALX_MISC3_25M_NOTO_INTNL BIT(0)