Lines Matching refs:adapter
44 adapter_t *adapter; member
60 static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr, in tricn_write() argument
70 adapter->regs + A_ESPI_CMD_ADDR); in tricn_write()
71 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write()
74 busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY; in tricn_write()
78 pr_err("%s: TRICN write timed out\n", adapter->name); in tricn_write()
83 static int tricn_init(adapter_t *adapter) in tricn_init() argument
87 if (!(readl(adapter->regs + A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) { in tricn_init()
88 pr_err("%s: ESPI clock not ready\n", adapter->name); in tricn_init()
92 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); in tricn_init()
95 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81); in tricn_init()
96 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81); in tricn_init()
97 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81); in tricn_init()
100 tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1); in tricn_init()
102 tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1); in tricn_init()
104 tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); in tricn_init()
105 tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1); in tricn_init()
106 tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1); in tricn_init()
107 tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1); in tricn_init()
108 tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80); in tricn_init()
109 tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1); in tricn_init()
112 adapter->regs + A_ESPI_RX_RESET); in tricn_init()
119 u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
128 enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK; in t1_espi_intr_enable()
129 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_enable()
130 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
135 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_clear()
136 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_clear()
137 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); in t1_espi_intr_clear()
142 u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
144 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_disable()
145 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
150 u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_handler()
169 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_handler()
176 if (status && t1_is_T1B(espi->adapter)) in t1_espi_intr_handler()
178 writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_handler()
187 static void espi_setup_for_pm3393(adapter_t *adapter) in espi_setup_for_pm3393() argument
189 u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200; in espi_setup_for_pm3393()
191 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); in espi_setup_for_pm3393()
192 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1); in espi_setup_for_pm3393()
193 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); in espi_setup_for_pm3393()
194 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3); in espi_setup_for_pm3393()
195 writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_pm3393()
196 writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_pm3393()
197 writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH); in espi_setup_for_pm3393()
198 writel(0x08000008, adapter->regs + A_ESPI_TRAIN); in espi_setup_for_pm3393()
199 writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG); in espi_setup_for_pm3393()
202 static void espi_setup_for_vsc7321(adapter_t *adapter) in espi_setup_for_vsc7321() argument
204 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); in espi_setup_for_vsc7321()
205 writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1); in espi_setup_for_vsc7321()
206 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); in espi_setup_for_vsc7321()
207 writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_vsc7321()
208 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_vsc7321()
209 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); in espi_setup_for_vsc7321()
210 writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG); in espi_setup_for_vsc7321()
212 writel(0x08000008, adapter->regs + A_ESPI_TRAIN); in espi_setup_for_vsc7321()
218 static void espi_setup_for_ixf1010(adapter_t *adapter, int nports) in espi_setup_for_ixf1010() argument
220 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); in espi_setup_for_ixf1010()
222 if (is_T2(adapter)) { in espi_setup_for_ixf1010()
223 writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_ixf1010()
224 writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_ixf1010()
226 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_ixf1010()
227 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_ixf1010()
230 writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_ixf1010()
231 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_ixf1010()
233 writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG); in espi_setup_for_ixf1010()
240 adapter_t *adapter = espi->adapter; in t1_espi_init() local
243 writel(0, adapter->regs + A_ESPI_TRAIN); in t1_espi_init()
245 if (is_T2(adapter)) { in t1_espi_init()
248 V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_init()
250 adapter->regs + A_ESPI_MAXBURST1_MAXBURST2); in t1_espi_init()
252 writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2); in t1_espi_init()
255 espi_setup_for_pm3393(adapter); in t1_espi_init()
257 espi_setup_for_vsc7321(adapter); in t1_espi_init()
260 espi_setup_for_ixf1010(adapter, nports); in t1_espi_init()
265 adapter->regs + A_ESPI_FIFO_STATUS_ENABLE); in t1_espi_init()
267 if (is_T2(adapter)) { in t1_espi_init()
268 tricn_init(adapter); in t1_espi_init()
273 espi->misc_ctrl = readl(adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_init()
276 if (adapter->params.nports == 1) in t1_espi_init()
278 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_init()
290 struct peespi *t1_espi_create(adapter_t *adapter) in t1_espi_create() argument
295 espi->adapter = adapter; in t1_espi_create()
300 void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
302 struct peespi *espi = adapter->espi;
304 if (!is_T2(adapter))
309 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
314 u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait) in t1_espi_get_mon() argument
316 struct peespi *espi = adapter->espi; in t1_espi_get_mon()
319 if (!is_T2(adapter)) in t1_espi_get_mon()
331 adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon()
332 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
333 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon()
335 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
345 int t1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait) in t1_espi_get_mon_t204() argument
347 struct peespi *espi = adapter->espi; in t1_espi_get_mon_t204()
348 u8 i, nport = (u8)adapter->params.nports; in t1_espi_get_mon_t204()
359 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon_t204()
364 adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon_t204()
366 *valp = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon_t204()
369 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon_t204()