Lines Matching refs:t3_write_reg
187 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, 0); in enable_tx_fifo_drain()
188 t3_write_reg(adapter, A_XGM_TX_CTRL + pi->mac.offset, F_TXEN); in enable_tx_fifo_drain()
189 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, F_RXEN); in enable_tx_fifo_drain()
218 t3_write_reg(adap, in t3_os_link_fault()
272 t3_write_reg(adapter, in t3_os_link_changed()
605 t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | V_EGRCNTX(qs->txq[j].cntxt_id)); in ring_dbs()
812 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr); in tm_attr_show()
939 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus); in init_port_mtus()
1245 t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); in cxgb_up()
1295 t3_write_reg(adap, A_TP_INT_CAUSE, in cxgb_up()
1297 t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff); in cxgb_up()
2734 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, reset); in t3_adap_check_task()
2761 t3_write_reg(adapter, A_SG_INT_CAUSE, reset); in t3_adap_check_task()
2834 t3_write_reg(adapter, A_PL_INT_CAUSE0, F_T3DBG); in ext_intr_task()
2835 t3_write_reg(adapter, A_PL_INT_ENABLE0, in ext_intr_task()
2855 t3_write_reg(adapter, A_PL_INT_ENABLE0, in t3_os_ext_intr_handler()
2974 t3_write_reg(adapter, A_XGM_TX_CTRL, 0); in t3_fatal_err()
2975 t3_write_reg(adapter, A_XGM_RX_CTRL, 0); in t3_fatal_err()
2976 t3_write_reg(adapter, XGM_REG(A_XGM_TX_CTRL, 1), 0); in t3_fatal_err()
2977 t3_write_reg(adapter, XGM_REG(A_XGM_RX_CTRL, 1), 0); in t3_fatal_err()