Lines Matching refs:reg
46 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local
51 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; in ixgbe_dcb_config_rx_arbiter_82598()
52 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598()
54 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_rx_arbiter_82598()
56 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598()
58 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598()
60 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598()
62 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598()
69 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82598()
72 reg |= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598()
74 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); in ixgbe_dcb_config_rx_arbiter_82598()
77 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); in ixgbe_dcb_config_rx_arbiter_82598()
78 reg |= IXGBE_RDRXCTL_RDMTS_1_2; in ixgbe_dcb_config_rx_arbiter_82598()
79 reg |= IXGBE_RDRXCTL_MPBEN; in ixgbe_dcb_config_rx_arbiter_82598()
80 reg |= IXGBE_RDRXCTL_MCEN; in ixgbe_dcb_config_rx_arbiter_82598()
81 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); in ixgbe_dcb_config_rx_arbiter_82598()
83 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_dcb_config_rx_arbiter_82598()
85 reg &= ~IXGBE_RXCTRL_DMBYPS; in ixgbe_dcb_config_rx_arbiter_82598()
86 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); in ixgbe_dcb_config_rx_arbiter_82598()
104 u32 reg, max_credits; in ixgbe_dcb_config_tx_desc_arbiter_82598() local
107 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); in ixgbe_dcb_config_tx_desc_arbiter_82598()
110 reg &= ~IXGBE_DPMCS_ARBDIS; in ixgbe_dcb_config_tx_desc_arbiter_82598()
111 reg |= IXGBE_DPMCS_TSOEF; in ixgbe_dcb_config_tx_desc_arbiter_82598()
114 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); in ixgbe_dcb_config_tx_desc_arbiter_82598()
116 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); in ixgbe_dcb_config_tx_desc_arbiter_82598()
121 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; in ixgbe_dcb_config_tx_desc_arbiter_82598()
122 reg |= refill[i]; in ixgbe_dcb_config_tx_desc_arbiter_82598()
123 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT; in ixgbe_dcb_config_tx_desc_arbiter_82598()
126 reg |= IXGBE_TDTQ2TCCR_GSP; in ixgbe_dcb_config_tx_desc_arbiter_82598()
129 reg |= IXGBE_TDTQ2TCCR_LSP; in ixgbe_dcb_config_tx_desc_arbiter_82598()
131 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); in ixgbe_dcb_config_tx_desc_arbiter_82598()
150 u32 reg; in ixgbe_dcb_config_tx_data_arbiter_82598() local
153 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); in ixgbe_dcb_config_tx_data_arbiter_82598()
155 reg &= ~IXGBE_PDPMCS_ARBDIS; in ixgbe_dcb_config_tx_data_arbiter_82598()
157 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM); in ixgbe_dcb_config_tx_data_arbiter_82598()
159 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); in ixgbe_dcb_config_tx_data_arbiter_82598()
163 reg = refill[i]; in ixgbe_dcb_config_tx_data_arbiter_82598()
164 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT; in ixgbe_dcb_config_tx_data_arbiter_82598()
165 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT; in ixgbe_dcb_config_tx_data_arbiter_82598()
168 reg |= IXGBE_TDPT2TCCR_GSP; in ixgbe_dcb_config_tx_data_arbiter_82598()
171 reg |= IXGBE_TDPT2TCCR_LSP; in ixgbe_dcb_config_tx_data_arbiter_82598()
173 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); in ixgbe_dcb_config_tx_data_arbiter_82598()
177 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); in ixgbe_dcb_config_tx_data_arbiter_82598()
178 reg |= IXGBE_DTXCTL_ENDBUBD; in ixgbe_dcb_config_tx_data_arbiter_82598()
179 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); in ixgbe_dcb_config_tx_data_arbiter_82598()
193 u32 fcrtl, reg; in ixgbe_dcb_config_pfc_82598() local
197 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_pfc_82598()
198 reg &= ~IXGBE_RMCS_TFCE_802_3X; in ixgbe_dcb_config_pfc_82598()
199 reg |= IXGBE_RMCS_TFCE_PRIORITY; in ixgbe_dcb_config_pfc_82598()
200 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_pfc_82598()
203 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); in ixgbe_dcb_config_pfc_82598()
204 reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE); in ixgbe_dcb_config_pfc_82598()
207 reg |= IXGBE_FCTRL_RPFCE; in ixgbe_dcb_config_pfc_82598()
209 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); in ixgbe_dcb_config_pfc_82598()
220 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_dcb_config_pfc_82598()
222 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); in ixgbe_dcb_config_pfc_82598()
226 reg = hw->fc.pause_time * 0x00010001; in ixgbe_dcb_config_pfc_82598()
228 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); in ixgbe_dcb_config_pfc_82598()
246 u32 reg = 0; in ixgbe_dcb_config_tc_stats_82598() local
252 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); in ixgbe_dcb_config_tc_stats_82598()
253 reg |= ((0x1010101) * j); in ixgbe_dcb_config_tc_stats_82598()
254 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); in ixgbe_dcb_config_tc_stats_82598()
255 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); in ixgbe_dcb_config_tc_stats_82598()
256 reg |= ((0x1010101) * j); in ixgbe_dcb_config_tc_stats_82598()
257 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); in ixgbe_dcb_config_tc_stats_82598()
261 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); in ixgbe_dcb_config_tc_stats_82598()
262 reg |= ((0x1010101) * i); in ixgbe_dcb_config_tc_stats_82598()
263 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); in ixgbe_dcb_config_tc_stats_82598()