Lines Matching refs:ioaddr
24 static int sxgbe_dma_init(void __iomem *ioaddr, int fix_burst, int burst_map) in sxgbe_dma_init() argument
28 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
41 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
46 static void sxgbe_dma_channel_init(void __iomem *ioaddr, int cha_num, in sxgbe_dma_channel_init() argument
53 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
57 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
59 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
61 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
63 reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
65 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
70 ioaddr + SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num)); in sxgbe_dma_channel_init()
72 ioaddr + SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num)); in sxgbe_dma_channel_init()
75 ioaddr + SXGBE_DMA_CHA_RXDESC_HADD_REG(cha_num)); in sxgbe_dma_channel_init()
77 ioaddr + SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num)); in sxgbe_dma_channel_init()
85 ioaddr + SXGBE_DMA_CHA_TXDESC_TAILPTR_REG(cha_num)); in sxgbe_dma_channel_init()
89 ioaddr + SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num)); in sxgbe_dma_channel_init()
91 writel(t_rsize - 1, ioaddr + SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num)); in sxgbe_dma_channel_init()
92 writel(r_rsize - 1, ioaddr + SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num)); in sxgbe_dma_channel_init()
96 ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(cha_num)); in sxgbe_dma_channel_init()
99 static void sxgbe_enable_dma_transmission(void __iomem *ioaddr, int cha_num) in sxgbe_enable_dma_transmission() argument
103 tx_config = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_enable_dma_transmission()
105 writel(tx_config, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_enable_dma_transmission()
108 static void sxgbe_enable_dma_irq(void __iomem *ioaddr, int dma_cnum) in sxgbe_enable_dma_irq() argument
112 ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(dma_cnum)); in sxgbe_enable_dma_irq()
115 static void sxgbe_disable_dma_irq(void __iomem *ioaddr, int dma_cnum) in sxgbe_disable_dma_irq() argument
118 writel(0, ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(dma_cnum)); in sxgbe_disable_dma_irq()
121 static void sxgbe_dma_start_tx(void __iomem *ioaddr, int tchannels) in sxgbe_dma_start_tx() argument
127 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_start_tx()
130 ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_start_tx()
134 static void sxgbe_dma_start_tx_queue(void __iomem *ioaddr, int dma_cnum) in sxgbe_dma_start_tx_queue() argument
138 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_start_tx_queue()
140 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_start_tx_queue()
143 static void sxgbe_dma_stop_tx_queue(void __iomem *ioaddr, int dma_cnum) in sxgbe_dma_stop_tx_queue() argument
147 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_stop_tx_queue()
149 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_stop_tx_queue()
152 static void sxgbe_dma_stop_tx(void __iomem *ioaddr, int tchannels) in sxgbe_dma_stop_tx() argument
158 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_stop_tx()
160 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_stop_tx()
164 static void sxgbe_dma_start_rx(void __iomem *ioaddr, int rchannels) in sxgbe_dma_start_rx() argument
170 rx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); in sxgbe_dma_start_rx()
173 ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); in sxgbe_dma_start_rx()
177 static void sxgbe_dma_stop_rx(void __iomem *ioaddr, int rchannels) in sxgbe_dma_stop_rx() argument
183 rx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); in sxgbe_dma_stop_rx()
185 writel(rx_ctl_reg, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); in sxgbe_dma_stop_rx()
189 static int sxgbe_tx_dma_int_status(void __iomem *ioaddr, int channel_no, in sxgbe_tx_dma_int_status() argument
192 u32 int_status = readl(ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_tx_dma_int_status()
256 writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_tx_dma_int_status()
261 static int sxgbe_rx_dma_int_status(void __iomem *ioaddr, int channel_no, in sxgbe_rx_dma_int_status() argument
264 u32 int_status = readl(ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_rx_dma_int_status()
322 writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_rx_dma_int_status()
328 static void sxgbe_dma_rx_watchdog(void __iomem *ioaddr, u32 riwt) in sxgbe_dma_rx_watchdog() argument
334 ioaddr + SXGBE_DMA_CHA_INT_RXWATCHTMR_REG(que_num)); in sxgbe_dma_rx_watchdog()
338 static void sxgbe_enable_tso(void __iomem *ioaddr, u8 chan_num) in sxgbe_enable_tso() argument
342 ctrl = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num)); in sxgbe_enable_tso()
344 writel(ctrl, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num)); in sxgbe_enable_tso()