20 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)  in dwmac4_dma_axi()  argument
22 	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);  in dwmac4_dma_axi()
71 	writel(value, ioaddr + DMA_SYS_BUS_MODE);  in dwmac4_dma_axi()
74 static void dwmac4_dma_init_channel(void __iomem *ioaddr, int pbl,  in dwmac4_dma_init_channel()  argument
83 	value = readl(ioaddr + DMA_CHAN_CONTROL(channel));  in dwmac4_dma_init_channel()
85 	writel(value, ioaddr + DMA_CHAN_CONTROL(channel));  in dwmac4_dma_init_channel()
87 	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));  in dwmac4_dma_init_channel()
89 	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(channel));  in dwmac4_dma_init_channel()
91 	value = readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));  in dwmac4_dma_init_channel()
93 	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(channel));  in dwmac4_dma_init_channel()
96 	writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(channel));  in dwmac4_dma_init_channel()
98 	writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));  in dwmac4_dma_init_channel()
99 	writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));  in dwmac4_dma_init_channel()
102 static void dwmac4_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,  in dwmac4_dma_init()  argument
105 	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);  in dwmac4_dma_init()
119 	writel(value, ioaddr + DMA_SYS_BUS_MODE);  in dwmac4_dma_init()
122 		dwmac4_dma_init_channel(ioaddr, pbl, dma_tx, dma_rx, i);  in dwmac4_dma_init()
125 static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel)  in _dwmac4_dump_dma_regs()  argument
129 		 readl(ioaddr + DMA_CHAN_CONTROL(channel)));  in _dwmac4_dump_dma_regs()
131 		 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)));  in _dwmac4_dump_dma_regs()
133 		 readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)));  in _dwmac4_dump_dma_regs()
135 		 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)));  in _dwmac4_dump_dma_regs()
137 		 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)));  in _dwmac4_dump_dma_regs()
139 		 readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)));  in _dwmac4_dump_dma_regs()
141 		 readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)));  in _dwmac4_dump_dma_regs()
143 		 readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)));  in _dwmac4_dump_dma_regs()
145 		 readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)));  in _dwmac4_dump_dma_regs()
147 		 readl(ioaddr + DMA_CHAN_INTR_ENA(channel)));  in _dwmac4_dump_dma_regs()
149 		 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)));  in _dwmac4_dump_dma_regs()
151 		 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)));  in _dwmac4_dump_dma_regs()
153 		 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)));  in _dwmac4_dump_dma_regs()
155 		 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)));  in _dwmac4_dump_dma_regs()
157 		 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)));  in _dwmac4_dump_dma_regs()
159 		 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)));  in _dwmac4_dump_dma_regs()
161 		 readl(ioaddr + DMA_CHAN_STATUS(channel)));  in _dwmac4_dump_dma_regs()
164 static void dwmac4_dump_dma_regs(void __iomem *ioaddr)  in dwmac4_dump_dma_regs()  argument
171 		_dwmac4_dump_dma_regs(ioaddr, i);  in dwmac4_dump_dma_regs()
174 static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt)  in dwmac4_rx_watchdog()  argument
179 		writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(i));  in dwmac4_rx_watchdog()
182 static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode,  in dwmac4_dma_chan_op_mode()  argument
190 	mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_dma_chan_op_mode()
219 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_dma_chan_op_mode()
221 	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));  in dwmac4_dma_chan_op_mode()
240 	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));  in dwmac4_dma_chan_op_mode()
243 	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));  in dwmac4_dma_chan_op_mode()
245 	       ioaddr + MTL_CHAN_INT_CTRL(channel));  in dwmac4_dma_chan_op_mode()
248 static void dwmac4_dma_operation_mode(void __iomem *ioaddr, int txmode,  in dwmac4_dma_operation_mode()  argument
252 	dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0);  in dwmac4_dma_operation_mode()
255 static void dwmac4_get_hw_feature(void __iomem *ioaddr,  in dwmac4_get_hw_feature()  argument
258 	u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);  in dwmac4_get_hw_feature()
281 	hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);  in dwmac4_get_hw_feature()
285 	hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);  in dwmac4_get_hw_feature()
297 static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)  in dwmac4_enable_tso()  argument
303 		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));  in dwmac4_enable_tso()
305 		       ioaddr + DMA_CHAN_TX_CONTROL(chan));  in dwmac4_enable_tso()
308 		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));  in dwmac4_enable_tso()
310 		       ioaddr + DMA_CHAN_TX_CONTROL(chan));  in dwmac4_enable_tso()