115 	int iobase;  member
164 #define RBR(iobase)	(iobase+0)  argument
165 #define THR(iobase)	(iobase+0)  argument
166 #define IER(iobase)	(iobase+1)  argument
167 #define IIR(iobase)	(iobase+2)  argument
168 #define FCR(iobase)	(iobase+2)  argument
169 #define LCR(iobase)	(iobase+3)  argument
170 #define MCR(iobase)	(iobase+4)  argument
171 #define LSR(iobase)	(iobase+5)  argument
172 #define MSR(iobase)	(iobase+6)  argument
173 #define SCR(iobase)	(iobase+7)  argument
174 #define DLL(iobase)	(iobase+0)  argument
175 #define DLM(iobase)	(iobase+1)  argument
306 static void fpga_reset(int iobase)  in fpga_reset()  argument
308 	outb(0, IER(iobase));  in fpga_reset()
309 	outb(LCR_DLAB | LCR_BIT5, LCR(iobase));  in fpga_reset()
310 	outb(1, DLL(iobase));  in fpga_reset()
311 	outb(0, DLM(iobase));  in fpga_reset()
313 	outb(LCR_BIT5, LCR(iobase));  in fpga_reset()
314 	inb(LSR(iobase));  in fpga_reset()
315 	inb(MSR(iobase));  in fpga_reset()
317 	outb(MCR_OUT1 | MCR_OUT2, MCR(iobase));  in fpga_reset()
320 	outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase));  in fpga_reset()
328 static int fpga_write(int iobase, unsigned char wrd)  in fpga_write()  argument
336 		outb(bit | MCR_OUT1 | MCR_OUT2, MCR(iobase));  in fpga_write()
338 		outb(0xfc, THR(iobase));  in fpga_write()
339 		while ((inb(LSR(iobase)) & LSR_TSRE) == 0)  in fpga_write()
444 static int fpga_download(int iobase, int bitrate)  in fpga_download()  argument
453 	fpga_reset(iobase);  in fpga_download()
455 		if (fpga_write(iobase, pbits[i])) {  in fpga_download()
461 	fpga_write(iobase, 0xFF);  in fpga_download()
462 	rc = inb(MSR(iobase));		/* check DONE signal */  in fpga_download()
509 static enum uart yam_check_uart(unsigned int iobase)  in yam_check_uart()  argument
516 	b1 = inb(MCR(iobase));  in yam_check_uart()
517 	outb(b1 | 0x10, MCR(iobase));	/* loopback mode */  in yam_check_uart()
518 	b2 = inb(MSR(iobase));  in yam_check_uart()
519 	outb(0x1a, MCR(iobase));  in yam_check_uart()
520 	b3 = inb(MSR(iobase)) & 0xf0;  in yam_check_uart()
521 	outb(b1, MCR(iobase));		/* restore old values */  in yam_check_uart()
522 	outb(b2, MSR(iobase));  in yam_check_uart()
525 	inb(RBR(iobase));  in yam_check_uart()
526 	inb(RBR(iobase));  in yam_check_uart()
527 	outb(0x01, FCR(iobase));	/* enable FIFOs */  in yam_check_uart()
528 	u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];  in yam_check_uart()
530 		outb(0x5a, SCR(iobase));  in yam_check_uart()
531 		b1 = inb(SCR(iobase));  in yam_check_uart()
532 		outb(0xa5, SCR(iobase));  in yam_check_uart()
533 		b2 = inb(SCR(iobase));  in yam_check_uart()
819 	seq_printf(seq, "  IoBase   0x%x\n", yp->iobase);  in yam_seq_show()
1010 			yp->iobase = yi.cfg.iobase;  in yam_ioctl()
1011 			dev->base_addr = yi.cfg.iobase;  in yam_ioctl()
1065 		yi.cfg.iobase = yp->iobase;  in yam_ioctl()
1115 	yp->iobase = 0;  in yam_setup()
1125 	dev->base_addr = yp->iobase;  in yam_setup()