Lines Matching refs:iobase
210 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
360 static inline void register_bank(int iobase, int bank) in register_bank() argument
362 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)), in register_bank()
363 iobase + IRCC_MASTER); in register_bank()
755 int iobase = self->io.fir_base; in smsc_ircc_init_chip() local
757 register_bank(iobase, 0); in smsc_ircc_init_chip()
758 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); in smsc_ircc_init_chip()
759 outb(0x00, iobase + IRCC_MASTER); in smsc_ircc_init_chip()
761 register_bank(iobase, 1); in smsc_ircc_init_chip()
762 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A), in smsc_ircc_init_chip()
763 iobase + IRCC_SCE_CFGA); in smsc_ircc_init_chip()
766 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), in smsc_ircc_init_chip()
767 iobase + IRCC_SCE_CFGB); in smsc_ircc_init_chip()
769 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), in smsc_ircc_init_chip()
770 iobase + IRCC_SCE_CFGB); in smsc_ircc_init_chip()
772 (void) inb(iobase + IRCC_FIFO_THRESHOLD); in smsc_ircc_init_chip()
773 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD); in smsc_ircc_init_chip()
775 register_bank(iobase, 4); in smsc_ircc_init_chip()
776 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL); in smsc_ircc_init_chip()
778 register_bank(iobase, 0); in smsc_ircc_init_chip()
779 outb(0, iobase + IRCC_LCR_A); in smsc_ircc_init_chip()
784 outb(0x00, iobase + IRCC_MASTER); in smsc_ircc_init_chip()
1134 int iobase; in smsc_ircc_set_sir_speed() local
1142 iobase = self->io.sir_base; in smsc_ircc_set_sir_speed()
1148 outb(0, iobase + UART_IER); in smsc_ircc_set_sir_speed()
1165 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */ in smsc_ircc_set_sir_speed()
1166 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */ in smsc_ircc_set_sir_speed()
1167 outb(divisor >> 8, iobase + UART_DLM); in smsc_ircc_set_sir_speed()
1168 outb(lcr, iobase + UART_LCR); /* Set 8N1 */ in smsc_ircc_set_sir_speed()
1169 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */ in smsc_ircc_set_sir_speed()
1172 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER); in smsc_ircc_set_sir_speed()
1255 int iobase = self->io.fir_base; in smsc_ircc_dma_xmit() local
1261 register_bank(iobase, 0); in smsc_ircc_dma_xmit()
1262 outb(0x00, iobase + IRCC_LCR_B); in smsc_ircc_dma_xmit()
1264 register_bank(iobase, 1); in smsc_ircc_dma_xmit()
1265 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, in smsc_ircc_dma_xmit()
1266 iobase + IRCC_SCE_CFGB); in smsc_ircc_dma_xmit()
1271 register_bank(iobase, 4); in smsc_ircc_dma_xmit()
1272 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO); in smsc_ircc_dma_xmit()
1273 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0; in smsc_ircc_dma_xmit()
1274 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI); in smsc_ircc_dma_xmit()
1277 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI); in smsc_ircc_dma_xmit()
1278 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO); in smsc_ircc_dma_xmit()
1283 register_bank(iobase, 1); in smsc_ircc_dma_xmit()
1284 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | in smsc_ircc_dma_xmit()
1285 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); in smsc_ircc_dma_xmit()
1293 register_bank(iobase, 0); in smsc_ircc_dma_xmit()
1294 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); in smsc_ircc_dma_xmit()
1295 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); in smsc_ircc_dma_xmit()
1298 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B); in smsc_ircc_dma_xmit()
1310 int iobase = self->io.fir_base; in smsc_ircc_dma_xmit_complete() local
1315 register_bank(iobase, 0); in smsc_ircc_dma_xmit_complete()
1316 outb(0x00, iobase + IRCC_LCR_B); in smsc_ircc_dma_xmit_complete()
1318 register_bank(iobase, 1); in smsc_ircc_dma_xmit_complete()
1319 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, in smsc_ircc_dma_xmit_complete()
1320 iobase + IRCC_SCE_CFGB); in smsc_ircc_dma_xmit_complete()
1323 register_bank(iobase, 0); in smsc_ircc_dma_xmit_complete()
1324 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) { in smsc_ircc_dma_xmit_complete()
1329 register_bank(iobase, 0); in smsc_ircc_dma_xmit_complete()
1330 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER); in smsc_ircc_dma_xmit_complete()
1331 outb(0x00, iobase + IRCC_MASTER); in smsc_ircc_dma_xmit_complete()
1355 int iobase = self->io.fir_base; in smsc_ircc_dma_receive() local
1358 register_bank(iobase, 1); in smsc_ircc_dma_receive()
1359 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, in smsc_ircc_dma_receive()
1360 iobase + IRCC_SCE_CFGB); in smsc_ircc_dma_receive()
1364 register_bank(iobase, 0); in smsc_ircc_dma_receive()
1365 outb(0x00, iobase + IRCC_LCR_B); in smsc_ircc_dma_receive()
1368 register_bank(iobase, 1); in smsc_ircc_dma_receive()
1369 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, in smsc_ircc_dma_receive()
1370 iobase + IRCC_SCE_CFGB); in smsc_ircc_dma_receive()
1376 register_bank(iobase, 4); in smsc_ircc_dma_receive()
1377 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI); in smsc_ircc_dma_receive()
1378 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO); in smsc_ircc_dma_receive()
1385 register_bank(iobase, 1); in smsc_ircc_dma_receive()
1386 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | in smsc_ircc_dma_receive()
1387 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); in smsc_ircc_dma_receive()
1390 register_bank(iobase, 0); in smsc_ircc_dma_receive()
1391 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); in smsc_ircc_dma_receive()
1392 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); in smsc_ircc_dma_receive()
1395 register_bank(iobase, 0); in smsc_ircc_dma_receive()
1397 iobase + IRCC_LCR_B); in smsc_ircc_dma_receive()
1412 int iobase = self->io.fir_base; in smsc_ircc_dma_receive_complete() local
1414 register_bank(iobase, 0); in smsc_ircc_dma_receive_complete()
1419 register_bank(iobase, 0); in smsc_ircc_dma_receive_complete()
1420 outb(0x00, iobase + IRCC_LCR_B); in smsc_ircc_dma_receive_complete()
1422 register_bank(iobase, 0); in smsc_ircc_dma_receive_complete()
1423 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR); in smsc_ircc_dma_receive_complete()
1424 lsr= inb(iobase + IRCC_LSR); in smsc_ircc_dma_receive_complete()
1425 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08; in smsc_ircc_dma_receive_complete()
1481 int iobase; in smsc_ircc_sir_receive() local
1485 iobase = self->io.sir_base; in smsc_ircc_sir_receive()
1493 inb(iobase + UART_RX)); in smsc_ircc_sir_receive()
1500 } while (inb(iobase + UART_LSR) & UART_LSR_DR); in smsc_ircc_sir_receive()
1514 int iobase, iir, lcra, lsr; in smsc_ircc_interrupt() local
1526 iobase = self->io.fir_base; in smsc_ircc_interrupt()
1528 register_bank(iobase, 0); in smsc_ircc_interrupt()
1529 iir = inb(iobase + IRCC_IIR); in smsc_ircc_interrupt()
1535 outb(0, iobase + IRCC_IER); in smsc_ircc_interrupt()
1536 lcra = inb(iobase + IRCC_LCR_A); in smsc_ircc_interrupt()
1537 lsr = inb(iobase + IRCC_LSR); in smsc_ircc_interrupt()
1556 register_bank(iobase, 0); in smsc_ircc_interrupt()
1557 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); in smsc_ircc_interrupt()
1574 int iobase; in smsc_ircc_interrupt_sir() local
1580 iobase = self->io.sir_base; in smsc_ircc_interrupt_sir()
1582 iir = inb(iobase + UART_IIR) & UART_IIR_ID; in smsc_ircc_interrupt_sir()
1587 lsr = inb(iobase + UART_LSR); in smsc_ircc_interrupt_sir()
1590 __func__, iir, lsr, iobase); in smsc_ircc_interrupt_sir()
1615 iir = inb(iobase + UART_IIR) & UART_IIR_ID; in smsc_ircc_interrupt_sir()
1674 int iobase = self->io.fir_base; in smsc_ircc_stop_interrupts() local
1679 register_bank(iobase, 0); in smsc_ircc_stop_interrupts()
1680 outb(0, iobase + IRCC_IER); in smsc_ircc_stop_interrupts()
1681 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); in smsc_ircc_stop_interrupts()
1682 outb(0x00, iobase + IRCC_MASTER); in smsc_ircc_stop_interrupts()
1936 int iobase; in smsc_ircc_sir_stop() local
1939 iobase = self->io.sir_base; in smsc_ircc_sir_stop()
1942 outb(0, iobase + UART_MCR); in smsc_ircc_sir_stop()
1945 outb(0, iobase + UART_IER); in smsc_ircc_sir_stop()
1959 int iobase; in smsc_ircc_sir_write_wakeup() local
1966 iobase = self->io.sir_base; in smsc_ircc_sir_write_wakeup()
1971 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size, in smsc_ircc_sir_write_wakeup()
2005 outb(fcr, iobase + UART_FCR); in smsc_ircc_sir_write_wakeup()
2008 outb(UART_IER_RDI, iobase + UART_IER); in smsc_ircc_sir_write_wakeup()
2019 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len) in smsc_ircc_sir_write() argument
2024 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) { in smsc_ircc_sir_write()
2033 outb(buf[actual], iobase + UART_TX); in smsc_ircc_sir_write()
2118 int iobase = self->io.sir_base; in smsc_ircc_sir_wait_hw_transmitter_finish() local
2122 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT)) in smsc_ircc_sir_wait_hw_transmitter_finish()
2531 unsigned short iobase = conf->cfg_base; in preconfigure_smsc_chip() local
2534 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state in preconfigure_smsc_chip()
2535 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID in preconfigure_smsc_chip()
2536 tmpbyte = inb(iobase +1); // Read device ID in preconfigure_smsc_chip()
2541 outb(0x24, iobase); // select CR24 - UART1 base addr in preconfigure_smsc_chip()
2542 outb(0x00, iobase + 1); // disable UART1 in preconfigure_smsc_chip()
2543 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr in preconfigure_smsc_chip()
2544 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8 in preconfigure_smsc_chip()
2545 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2553 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select in preconfigure_smsc_chip()
2554 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2557 outb(tmpbyte, iobase + 1); in preconfigure_smsc_chip()
2558 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; in preconfigure_smsc_chip()
2565 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr in preconfigure_smsc_chip()
2566 outb((conf->fir_io >> 3), iobase + 1); in preconfigure_smsc_chip()
2567 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2574 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select in preconfigure_smsc_chip()
2575 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA in preconfigure_smsc_chip()
2576 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK; in preconfigure_smsc_chip()
2582 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode in preconfigure_smsc_chip()
2583 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2586 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed in preconfigure_smsc_chip()
2588 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel in preconfigure_smsc_chip()
2589 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2590 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down in preconfigure_smsc_chip()
2593 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux in preconfigure_smsc_chip()
2594 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2595 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port in preconfigure_smsc_chip()
2597 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power in preconfigure_smsc_chip()
2598 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2599 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down in preconfigure_smsc_chip()
2601 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle in preconfigure_smsc_chip()
2602 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2603 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done in preconfigure_smsc_chip()
2605 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration in preconfigure_smsc_chip()