Lines Matching refs:REG_WRITE
73 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
218 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
250 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
294 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar5008_hw_cmn_spur_mitigate()
295 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar5008_hw_cmn_spur_mitigate()
327 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
328 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
338 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
339 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
349 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
350 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
360 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
361 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
371 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
372 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
382 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
383 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
393 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
394 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
404 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
405 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
452 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); in ar5008_hw_spur_mitigate()
459 REG_WRITE(ah, AR_PHY_SPUR_REG, new); in ar5008_hw_spur_mitigate()
470 REG_WRITE(ah, AR_PHY_TIMING11, new); in ar5008_hw_spur_mitigate()
569 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar5008_hw_init_bb()
588 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); in ar5008_hw_init_chain_masks()
589 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); in ar5008_hw_init_chain_masks()
596 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ar5008_hw_init_chain_masks()
597 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ar5008_hw_init_chain_masks()
604 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); in ar5008_hw_init_chain_masks()
613 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
648 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); in ar5008_hw_override_ini()
657 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); in ar5008_hw_override_ini()
666 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); in ar5008_hw_override_ini()
691 REG_WRITE(ah, AR_PHY_TURBO, phymode); in ar5008_hw_set_channel_regs()
697 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar5008_hw_set_channel_regs()
698 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar5008_hw_set_channel_regs()
723 REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar5008_hw_process_ini()
726 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); in ar5008_hw_process_ini()
731 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); in ar5008_hw_process_ini()
742 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
774 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
827 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar5008_hw_set_rfmode()
832 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar5008_hw_mark_phy_inactive()
871 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); in ar5008_hw_rfbus_req()
882 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ar5008_hw_rfbus_done()
890 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ar5008_restore_chainmask()
891 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ar5008_restore_chainmask()
1238 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); in ar5008_hw_set_radar_params()
1239 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); in ar5008_hw_set_radar_params()