32 	REG_WRITE(ah, AR_IMR_S0,  in ath9k_hw_set_txq_interrupts()
35 	REG_WRITE(ah, AR_IMR_S1,  in ath9k_hw_set_txq_interrupts()
41 	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);  in ath9k_hw_set_txq_interrupts()
54 	REG_WRITE(ah, AR_QTXDP(q), txdp);  in ath9k_hw_puttxbuf()
61 	REG_WRITE(ah, AR_Q_TXE, 1 << q);  in ath9k_hw_txstart()
123 		REG_WRITE(ah, AR_TXCFG,  in ath9k_hw_updatetxtriglevel()
146 	REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);  in ath9k_hw_abort_tx_dma()
166 	REG_WRITE(ah, AR_Q_TXD, 0);  in ath9k_hw_abort_tx_dma()
177 	REG_WRITE(ah, AR_Q_TXD, 1 << q);  in ath9k_hw_stop_dma_queue()
187 	REG_WRITE(ah, AR_Q_TXD, 0);  in ath9k_hw_stop_dma_queue()
390 	REG_WRITE(ah, AR_DLCL_IFS(q),  in ath9k_hw_resettxqueue()
395 	REG_WRITE(ah, AR_DRETRY_LIMIT(q),  in ath9k_hw_resettxqueue()
400 	REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);  in ath9k_hw_resettxqueue()
403 		REG_WRITE(ah, AR_DMISC(q),  in ath9k_hw_resettxqueue()
406 		REG_WRITE(ah, AR_DMISC(q),  in ath9k_hw_resettxqueue()
410 		REG_WRITE(ah, AR_QCBRCFG(q),  in ath9k_hw_resettxqueue()
418 		REG_WRITE(ah, AR_QRDYTIMECFG(q),  in ath9k_hw_resettxqueue()
423 	REG_WRITE(ah, AR_DCHNTIME(q),  in ath9k_hw_resettxqueue()
463 			REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)  in ath9k_hw_resettxqueue()
478 		REG_WRITE(ah, AR_QRDYTIMECFG(q),  in ath9k_hw_resettxqueue()
505 		REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);  in ath9k_hw_resettxqueue()
670 	REG_WRITE(ah, AR_RXDP, rxdp);  in ath9k_hw_putrxbuf()
700 	REG_WRITE(ah, AR_MACMISC,  in ath9k_hw_stopdmarecv()
705 	REG_WRITE(ah, AR_CR, AR_CR_RXD);  in ath9k_hw_stopdmarecv()
785 	REG_WRITE(ah, AR_IER, AR_IER_DISABLE);  in ath9k_hw_kill_interrupts()
788 		REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);  in ath9k_hw_kill_interrupts()
791 		REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);  in ath9k_hw_kill_interrupts()
824 	REG_WRITE(ah, AR_IER, AR_IER_ENABLE);  in __ath9k_hw_enable_interrupts()
826 		REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask);  in __ath9k_hw_enable_interrupts()
827 		REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask);  in __ath9k_hw_enable_interrupts()
829 		REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);  in __ath9k_hw_enable_interrupts()
830 		REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);  in __ath9k_hw_enable_interrupts()
951 	REG_WRITE(ah, AR_IMR, mask);  in ath9k_hw_set_interrupts()
967 	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);  in ath9k_hw_set_interrupts()
997 		REG_WRITE(ah, AR_D_TXBLK_BASE, filter);  in ath9k_hw_set_tx_filter()