Lines Matching refs:reg
59 u32 reg; in rt2400pci_bbp_write() local
67 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_write()
68 reg = 0; in rt2400pci_bbp_write()
69 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2400pci_bbp_write()
70 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2400pci_bbp_write()
71 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2400pci_bbp_write()
72 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2400pci_bbp_write()
74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_write()
83 u32 reg; in rt2400pci_bbp_read() local
95 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_read()
96 reg = 0; in rt2400pci_bbp_read()
97 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2400pci_bbp_read()
98 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2400pci_bbp_read()
99 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); in rt2400pci_bbp_read()
101 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_read()
103 WAIT_FOR_BBP(rt2x00dev, ®); in rt2400pci_bbp_read()
106 *value = rt2x00_get_field32(reg, BBPCSR_VALUE); in rt2400pci_bbp_read()
114 u32 reg; in rt2400pci_rf_write() local
122 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt2400pci_rf_write()
123 reg = 0; in rt2400pci_rf_write()
124 rt2x00_set_field32(®, RFCSR_VALUE, value); in rt2400pci_rf_write()
125 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); in rt2400pci_rf_write()
126 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); in rt2400pci_rf_write()
127 rt2x00_set_field32(®, RFCSR_BUSY, 1); in rt2400pci_rf_write()
129 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); in rt2400pci_rf_write()
139 u32 reg; in rt2400pci_eepromregister_read() local
141 rt2x00mmio_register_read(rt2x00dev, CSR21, ®); in rt2400pci_eepromregister_read()
143 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); in rt2400pci_eepromregister_read()
144 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); in rt2400pci_eepromregister_read()
146 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); in rt2400pci_eepromregister_read()
148 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); in rt2400pci_eepromregister_read()
154 u32 reg = 0; in rt2400pci_eepromregister_write() local
156 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); in rt2400pci_eepromregister_write()
157 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); in rt2400pci_eepromregister_write()
158 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, in rt2400pci_eepromregister_write()
160 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, in rt2400pci_eepromregister_write()
163 rt2x00mmio_register_write(rt2x00dev, CSR21, reg); in rt2400pci_eepromregister_write()
203 u32 reg; in rt2400pci_rfkill_poll() local
205 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®); in rt2400pci_rfkill_poll()
206 return rt2x00_get_field32(reg, GPIOCSR_VAL0); in rt2400pci_rfkill_poll()
216 u32 reg; in rt2400pci_brightness_set() local
218 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®); in rt2400pci_brightness_set()
221 rt2x00_set_field32(®, LEDCSR_LINK, enabled); in rt2400pci_brightness_set()
223 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); in rt2400pci_brightness_set()
225 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2400pci_brightness_set()
234 u32 reg; in rt2400pci_blink_set() local
236 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®); in rt2400pci_blink_set()
237 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); in rt2400pci_blink_set()
238 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); in rt2400pci_blink_set()
239 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2400pci_blink_set()
262 u32 reg; in rt2400pci_config_filter() local
269 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); in rt2400pci_config_filter()
270 rt2x00_set_field32(®, RXCSR0_DROP_CRC, in rt2400pci_config_filter()
272 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, in rt2400pci_config_filter()
274 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, in rt2400pci_config_filter()
276 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, in rt2400pci_config_filter()
278 rt2x00_set_field32(®, RXCSR0_DROP_TODS, in rt2400pci_config_filter()
281 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); in rt2400pci_config_filter()
282 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_config_filter()
291 u32 reg; in rt2400pci_config_intf() local
298 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, ®); in rt2400pci_config_intf()
299 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); in rt2400pci_config_intf()
300 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); in rt2400pci_config_intf()
305 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2400pci_config_intf()
306 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); in rt2400pci_config_intf()
307 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_config_intf()
325 u32 reg; in rt2400pci_config_erp() local
333 rt2x00mmio_register_read(rt2x00dev, TXCSR1, ®); in rt2400pci_config_erp()
334 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x1ff); in rt2400pci_config_erp()
335 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0x13a); in rt2400pci_config_erp()
336 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); in rt2400pci_config_erp()
337 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); in rt2400pci_config_erp()
338 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); in rt2400pci_config_erp()
340 rt2x00mmio_register_read(rt2x00dev, ARCSR2, ®); in rt2400pci_config_erp()
341 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); in rt2400pci_config_erp()
342 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); in rt2400pci_config_erp()
343 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
345 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); in rt2400pci_config_erp()
347 rt2x00mmio_register_read(rt2x00dev, ARCSR3, ®); in rt2400pci_config_erp()
348 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); in rt2400pci_config_erp()
349 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); in rt2400pci_config_erp()
350 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
352 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); in rt2400pci_config_erp()
354 rt2x00mmio_register_read(rt2x00dev, ARCSR4, ®); in rt2400pci_config_erp()
355 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); in rt2400pci_config_erp()
356 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); in rt2400pci_config_erp()
357 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
359 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); in rt2400pci_config_erp()
361 rt2x00mmio_register_read(rt2x00dev, ARCSR5, ®); in rt2400pci_config_erp()
362 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); in rt2400pci_config_erp()
363 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); in rt2400pci_config_erp()
364 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
366 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); in rt2400pci_config_erp()
373 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); in rt2400pci_config_erp()
374 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); in rt2400pci_config_erp()
375 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_erp()
377 rt2x00mmio_register_read(rt2x00dev, CSR18, ®); in rt2400pci_config_erp()
378 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); in rt2400pci_config_erp()
379 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); in rt2400pci_config_erp()
380 rt2x00mmio_register_write(rt2x00dev, CSR18, reg); in rt2400pci_config_erp()
382 rt2x00mmio_register_read(rt2x00dev, CSR19, ®); in rt2400pci_config_erp()
383 rt2x00_set_field32(®, CSR19_DIFS, erp->difs); in rt2400pci_config_erp()
384 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); in rt2400pci_config_erp()
385 rt2x00mmio_register_write(rt2x00dev, CSR19, reg); in rt2400pci_config_erp()
389 rt2x00mmio_register_read(rt2x00dev, CSR12, ®); in rt2400pci_config_erp()
390 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, in rt2400pci_config_erp()
392 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, in rt2400pci_config_erp()
394 rt2x00mmio_register_write(rt2x00dev, CSR12, reg); in rt2400pci_config_erp()
509 u32 reg; in rt2400pci_config_retry_limit() local
511 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); in rt2400pci_config_retry_limit()
512 rt2x00_set_field32(®, CSR11_LONG_RETRY, in rt2400pci_config_retry_limit()
514 rt2x00_set_field32(®, CSR11_SHORT_RETRY, in rt2400pci_config_retry_limit()
516 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_retry_limit()
525 u32 reg; in rt2400pci_config_ps() local
528 rt2x00mmio_register_read(rt2x00dev, CSR20, ®); in rt2400pci_config_ps()
529 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, in rt2400pci_config_ps()
531 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, in rt2400pci_config_ps()
535 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2400pci_config_ps()
536 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
538 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); in rt2400pci_config_ps()
539 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
541 rt2x00mmio_register_read(rt2x00dev, CSR20, ®); in rt2400pci_config_ps()
542 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2400pci_config_ps()
543 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
567 u32 reg; in rt2400pci_config_cw() local
569 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); in rt2400pci_config_cw()
570 rt2x00_set_field32(®, CSR11_CWMIN, cw_min); in rt2400pci_config_cw()
571 rt2x00_set_field32(®, CSR11_CWMAX, cw_max); in rt2400pci_config_cw()
572 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_cw()
581 u32 reg; in rt2400pci_link_stats() local
587 rt2x00mmio_register_read(rt2x00dev, CNT0, ®); in rt2400pci_link_stats()
588 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); in rt2400pci_link_stats()
638 u32 reg; in rt2400pci_start_queue() local
642 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); in rt2400pci_start_queue()
643 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); in rt2400pci_start_queue()
644 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_start_queue()
647 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2400pci_start_queue()
648 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); in rt2400pci_start_queue()
649 rt2x00_set_field32(®, CSR14_TBCN, 1); in rt2400pci_start_queue()
650 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2400pci_start_queue()
651 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_start_queue()
661 u32 reg; in rt2400pci_kick_queue() local
665 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2400pci_kick_queue()
666 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); in rt2400pci_kick_queue()
667 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
670 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2400pci_kick_queue()
671 rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); in rt2400pci_kick_queue()
672 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
675 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2400pci_kick_queue()
676 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); in rt2400pci_kick_queue()
677 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
687 u32 reg; in rt2400pci_stop_queue() local
693 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2400pci_stop_queue()
694 rt2x00_set_field32(®, TXCSR0_ABORT, 1); in rt2400pci_stop_queue()
695 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_stop_queue()
698 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); in rt2400pci_stop_queue()
699 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); in rt2400pci_stop_queue()
700 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_stop_queue()
703 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2400pci_stop_queue()
704 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2400pci_stop_queue()
705 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2400pci_stop_queue()
706 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2400pci_stop_queue()
707 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_stop_queue()
768 u32 reg; in rt2400pci_init_queues() local
773 rt2x00mmio_register_read(rt2x00dev, TXCSR2, ®); in rt2400pci_init_queues()
774 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); in rt2400pci_init_queues()
775 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); in rt2400pci_init_queues()
776 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); in rt2400pci_init_queues()
777 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); in rt2400pci_init_queues()
778 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); in rt2400pci_init_queues()
781 rt2x00mmio_register_read(rt2x00dev, TXCSR3, ®); in rt2400pci_init_queues()
782 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, in rt2400pci_init_queues()
784 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); in rt2400pci_init_queues()
787 rt2x00mmio_register_read(rt2x00dev, TXCSR5, ®); in rt2400pci_init_queues()
788 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, in rt2400pci_init_queues()
790 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); in rt2400pci_init_queues()
793 rt2x00mmio_register_read(rt2x00dev, TXCSR4, ®); in rt2400pci_init_queues()
794 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, in rt2400pci_init_queues()
796 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); in rt2400pci_init_queues()
799 rt2x00mmio_register_read(rt2x00dev, TXCSR6, ®); in rt2400pci_init_queues()
800 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, in rt2400pci_init_queues()
802 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); in rt2400pci_init_queues()
804 rt2x00mmio_register_read(rt2x00dev, RXCSR1, ®); in rt2400pci_init_queues()
805 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); in rt2400pci_init_queues()
806 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); in rt2400pci_init_queues()
807 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); in rt2400pci_init_queues()
810 rt2x00mmio_register_read(rt2x00dev, RXCSR2, ®); in rt2400pci_init_queues()
811 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, in rt2400pci_init_queues()
813 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); in rt2400pci_init_queues()
820 u32 reg; in rt2400pci_init_registers() local
827 rt2x00mmio_register_read(rt2x00dev, TIMECSR, ®); in rt2400pci_init_registers()
828 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); in rt2400pci_init_registers()
829 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); in rt2400pci_init_registers()
830 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); in rt2400pci_init_registers()
831 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); in rt2400pci_init_registers()
833 rt2x00mmio_register_read(rt2x00dev, CSR9, ®); in rt2400pci_init_registers()
834 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, in rt2400pci_init_registers()
836 rt2x00mmio_register_write(rt2x00dev, CSR9, reg); in rt2400pci_init_registers()
838 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2400pci_init_registers()
839 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2400pci_init_registers()
840 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); in rt2400pci_init_registers()
841 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2400pci_init_registers()
842 rt2x00_set_field32(®, CSR14_TCFP, 0); in rt2400pci_init_registers()
843 rt2x00_set_field32(®, CSR14_TATIMW, 0); in rt2400pci_init_registers()
844 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2400pci_init_registers()
845 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); in rt2400pci_init_registers()
846 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); in rt2400pci_init_registers()
847 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_init_registers()
851 rt2x00mmio_register_read(rt2x00dev, ARCSR0, ®); in rt2400pci_init_registers()
852 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133); in rt2400pci_init_registers()
853 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134); in rt2400pci_init_registers()
854 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136); in rt2400pci_init_registers()
855 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135); in rt2400pci_init_registers()
856 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg); in rt2400pci_init_registers()
858 rt2x00mmio_register_read(rt2x00dev, RXCSR3, ®); in rt2400pci_init_registers()
859 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/ in rt2400pci_init_registers()
860 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); in rt2400pci_init_registers()
861 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */ in rt2400pci_init_registers()
862 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); in rt2400pci_init_registers()
863 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */ in rt2400pci_init_registers()
864 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); in rt2400pci_init_registers()
865 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); in rt2400pci_init_registers()
875 rt2x00mmio_register_read(rt2x00dev, MACCSR2, ®); in rt2400pci_init_registers()
876 rt2x00_set_field32(®, MACCSR2_DELAY, 64); in rt2400pci_init_registers()
877 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); in rt2400pci_init_registers()
879 rt2x00mmio_register_read(rt2x00dev, RALINKCSR, ®); in rt2400pci_init_registers()
880 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); in rt2400pci_init_registers()
881 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154); in rt2400pci_init_registers()
882 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); in rt2400pci_init_registers()
883 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154); in rt2400pci_init_registers()
884 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); in rt2400pci_init_registers()
886 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); in rt2400pci_init_registers()
887 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); in rt2400pci_init_registers()
888 rt2x00_set_field32(®, CSR1_BBP_RESET, 0); in rt2400pci_init_registers()
889 rt2x00_set_field32(®, CSR1_HOST_READY, 0); in rt2400pci_init_registers()
890 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
892 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); in rt2400pci_init_registers()
893 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); in rt2400pci_init_registers()
894 rt2x00_set_field32(®, CSR1_HOST_READY, 1); in rt2400pci_init_registers()
895 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
902 rt2x00mmio_register_read(rt2x00dev, CNT0, ®); in rt2400pci_init_registers()
903 rt2x00mmio_register_read(rt2x00dev, CNT4, ®); in rt2400pci_init_registers()
969 u32 reg; in rt2400pci_toggle_irq() local
977 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); in rt2400pci_toggle_irq()
978 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_toggle_irq()
987 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2400pci_toggle_irq()
988 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); in rt2400pci_toggle_irq()
989 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); in rt2400pci_toggle_irq()
990 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); in rt2400pci_toggle_irq()
991 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); in rt2400pci_toggle_irq()
992 rt2x00_set_field32(®, CSR8_RXDONE, mask); in rt2400pci_toggle_irq()
993 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_toggle_irq()
1032 u32 reg, reg2; in rt2400pci_set_state() local
1040 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, ®); in rt2400pci_set_state()
1041 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); in rt2400pci_set_state()
1042 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); in rt2400pci_set_state()
1043 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); in rt2400pci_set_state()
1044 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); in rt2400pci_set_state()
1045 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2400pci_set_state()
1058 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2400pci_set_state()
1177 u32 reg; in rt2400pci_write_beacon() local
1183 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2400pci_write_beacon()
1184 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2400pci_write_beacon()
1185 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_write_beacon()
1194 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2400pci_write_beacon()
1208 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2400pci_write_beacon()
1209 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_write_beacon()
1315 u32 reg; in rt2400pci_enable_interrupt() local
1323 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2400pci_enable_interrupt()
1324 rt2x00_set_field32(®, irq_field, 0); in rt2400pci_enable_interrupt()
1325 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_enable_interrupt()
1333 u32 reg; in rt2400pci_txstatus_tasklet() local
1348 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2400pci_txstatus_tasklet()
1349 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); in rt2400pci_txstatus_tasklet()
1350 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); in rt2400pci_txstatus_tasklet()
1351 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); in rt2400pci_txstatus_tasklet()
1352 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_txstatus_tasklet()
1378 u32 reg, mask; in rt2400pci_interrupt() local
1384 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); in rt2400pci_interrupt()
1385 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_interrupt()
1387 if (!reg) in rt2400pci_interrupt()
1393 mask = reg; in rt2400pci_interrupt()
1398 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) in rt2400pci_interrupt()
1401 if (rt2x00_get_field32(reg, CSR7_RXDONE)) in rt2400pci_interrupt()
1404 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || in rt2400pci_interrupt()
1405 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || in rt2400pci_interrupt()
1406 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { in rt2400pci_interrupt()
1422 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2400pci_interrupt()
1423 reg |= mask; in rt2400pci_interrupt()
1424 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_interrupt()
1439 u32 reg; in rt2400pci_validate_eeprom() local
1443 rt2x00mmio_register_read(rt2x00dev, CSR21, ®); in rt2400pci_validate_eeprom()
1448 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? in rt2400pci_validate_eeprom()
1478 u32 reg; in rt2400pci_init_eeprom() local
1491 rt2x00mmio_register_read(rt2x00dev, CSR0, ®); in rt2400pci_init_eeprom()
1493 rt2x00_get_field32(reg, CSR0_REVISION)); in rt2400pci_init_eeprom()
1619 u32 reg; in rt2400pci_probe_hw() local
1636 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®); in rt2400pci_probe_hw()
1637 rt2x00_set_field32(®, GPIOCSR_DIR0, 1); in rt2400pci_probe_hw()
1638 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); in rt2400pci_probe_hw()
1696 u32 reg; in rt2400pci_get_tsf() local
1698 rt2x00mmio_register_read(rt2x00dev, CSR17, ®); in rt2400pci_get_tsf()
1699 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; in rt2400pci_get_tsf()
1700 rt2x00mmio_register_read(rt2x00dev, CSR16, ®); in rt2400pci_get_tsf()
1701 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); in rt2400pci_get_tsf()
1709 u32 reg; in rt2400pci_tx_last_beacon() local
1711 rt2x00mmio_register_read(rt2x00dev, CSR15, ®); in rt2400pci_tx_last_beacon()
1712 return rt2x00_get_field32(reg, CSR15_BEACON_SENT); in rt2400pci_tx_last_beacon()