Lines Matching refs:reg
68 u32 reg; in rt61pci_bbp_write() local
76 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_write()
77 reg = 0; in rt61pci_bbp_write()
78 rt2x00_set_field32(®, PHY_CSR3_VALUE, value); in rt61pci_bbp_write()
79 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); in rt61pci_bbp_write()
80 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); in rt61pci_bbp_write()
81 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); in rt61pci_bbp_write()
83 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_write()
92 u32 reg; in rt61pci_bbp_read() local
104 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_read()
105 reg = 0; in rt61pci_bbp_read()
106 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); in rt61pci_bbp_read()
107 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); in rt61pci_bbp_read()
108 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); in rt61pci_bbp_read()
110 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_read()
112 WAIT_FOR_BBP(rt2x00dev, ®); in rt61pci_bbp_read()
115 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); in rt61pci_bbp_read()
123 u32 reg; in rt61pci_rf_write() local
131 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt61pci_rf_write()
132 reg = 0; in rt61pci_rf_write()
133 rt2x00_set_field32(®, PHY_CSR4_VALUE, value); in rt61pci_rf_write()
134 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21); in rt61pci_rf_write()
135 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); in rt61pci_rf_write()
136 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); in rt61pci_rf_write()
138 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg); in rt61pci_rf_write()
149 u32 reg; in rt61pci_mcu_request() local
157 if (WAIT_FOR_MCU(rt2x00dev, ®)) { in rt61pci_mcu_request()
158 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); in rt61pci_mcu_request()
159 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); in rt61pci_mcu_request()
160 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); in rt61pci_mcu_request()
161 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); in rt61pci_mcu_request()
162 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); in rt61pci_mcu_request()
164 rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR, ®); in rt61pci_mcu_request()
165 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); in rt61pci_mcu_request()
166 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1); in rt61pci_mcu_request()
167 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg); in rt61pci_mcu_request()
177 u32 reg; in rt61pci_eepromregister_read() local
179 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); in rt61pci_eepromregister_read()
181 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); in rt61pci_eepromregister_read()
182 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); in rt61pci_eepromregister_read()
184 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); in rt61pci_eepromregister_read()
186 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); in rt61pci_eepromregister_read()
192 u32 reg = 0; in rt61pci_eepromregister_write() local
194 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); in rt61pci_eepromregister_write()
195 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); in rt61pci_eepromregister_write()
196 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, in rt61pci_eepromregister_write()
198 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, in rt61pci_eepromregister_write()
201 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); in rt61pci_eepromregister_write()
241 u32 reg; in rt61pci_rfkill_poll() local
243 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); in rt61pci_rfkill_poll()
244 return rt2x00_get_field32(reg, MAC_CSR13_VAL5); in rt61pci_rfkill_poll()
292 u32 reg; in rt61pci_blink_set() local
294 rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14, ®); in rt61pci_blink_set()
295 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); in rt61pci_blink_set()
296 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); in rt61pci_blink_set()
297 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg); in rt61pci_blink_set()
324 u32 reg; in rt61pci_config_shared_key() local
339 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, ®); in rt61pci_config_shared_key()
340 reg &= mask; in rt61pci_config_shared_key()
342 if (reg && reg == mask) in rt61pci_config_shared_key()
345 key->hw_key_idx += reg ? ffz(reg) : 0; in rt61pci_config_shared_key()
357 reg = SHARED_KEY_ENTRY(key->hw_key_idx); in rt61pci_config_shared_key()
358 rt2x00mmio_register_multiwrite(rt2x00dev, reg, in rt61pci_config_shared_key()
372 rt2x00mmio_register_read(rt2x00dev, SEC_CSR1, ®); in rt61pci_config_shared_key()
373 rt2x00_set_field32(®, field, crypto->cipher); in rt61pci_config_shared_key()
374 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg); in rt61pci_config_shared_key()
379 rt2x00mmio_register_read(rt2x00dev, SEC_CSR5, ®); in rt61pci_config_shared_key()
380 rt2x00_set_field32(®, field, crypto->cipher); in rt61pci_config_shared_key()
381 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg); in rt61pci_config_shared_key()
404 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, ®); in rt61pci_config_shared_key()
406 reg |= mask; in rt61pci_config_shared_key()
408 reg &= ~mask; in rt61pci_config_shared_key()
409 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, reg); in rt61pci_config_shared_key()
421 u32 reg; in rt61pci_config_pairwise_key() local
433 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, ®); in rt61pci_config_pairwise_key()
434 if (reg && reg == ~0) { in rt61pci_config_pairwise_key()
436 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, ®); in rt61pci_config_pairwise_key()
437 if (reg && reg == ~0) in rt61pci_config_pairwise_key()
441 key->hw_key_idx += reg ? ffz(reg) : 0; in rt61pci_config_pairwise_key()
457 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); in rt61pci_config_pairwise_key()
458 rt2x00mmio_register_multiwrite(rt2x00dev, reg, in rt61pci_config_pairwise_key()
461 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); in rt61pci_config_pairwise_key()
462 rt2x00mmio_register_multiwrite(rt2x00dev, reg, in rt61pci_config_pairwise_key()
470 rt2x00mmio_register_read(rt2x00dev, SEC_CSR4, ®); in rt61pci_config_pairwise_key()
471 reg |= (1 << crypto->bssidx); in rt61pci_config_pairwise_key()
472 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg); in rt61pci_config_pairwise_key()
495 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, ®); in rt61pci_config_pairwise_key()
497 reg |= mask; in rt61pci_config_pairwise_key()
499 reg &= ~mask; in rt61pci_config_pairwise_key()
500 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg); in rt61pci_config_pairwise_key()
504 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, ®); in rt61pci_config_pairwise_key()
506 reg |= mask; in rt61pci_config_pairwise_key()
508 reg &= ~mask; in rt61pci_config_pairwise_key()
509 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg); in rt61pci_config_pairwise_key()
518 u32 reg; in rt61pci_config_filter() local
526 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_config_filter()
527 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, in rt61pci_config_filter()
529 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, in rt61pci_config_filter()
531 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, in rt61pci_config_filter()
533 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, in rt61pci_config_filter()
535 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, in rt61pci_config_filter()
538 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); in rt61pci_config_filter()
539 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, in rt61pci_config_filter()
541 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); in rt61pci_config_filter()
542 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, in rt61pci_config_filter()
544 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_filter()
552 u32 reg; in rt61pci_config_intf() local
558 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_config_intf()
559 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); in rt61pci_config_intf()
560 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_intf()
564 reg = le32_to_cpu(conf->mac[1]); in rt61pci_config_intf()
565 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); in rt61pci_config_intf()
566 conf->mac[1] = cpu_to_le32(reg); in rt61pci_config_intf()
573 reg = le32_to_cpu(conf->bssid[1]); in rt61pci_config_intf()
574 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); in rt61pci_config_intf()
575 conf->bssid[1] = cpu_to_le32(reg); in rt61pci_config_intf()
587 u32 reg; in rt61pci_config_erp() local
589 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_config_erp()
590 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); in rt61pci_config_erp()
591 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); in rt61pci_config_erp()
592 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_erp()
595 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, ®); in rt61pci_config_erp()
596 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); in rt61pci_config_erp()
597 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, in rt61pci_config_erp()
599 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_erp()
607 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_config_erp()
608 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, in rt61pci_config_erp()
610 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_erp()
614 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, ®); in rt61pci_config_erp()
615 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); in rt61pci_config_erp()
616 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_config_erp()
618 rt2x00mmio_register_read(rt2x00dev, MAC_CSR8, ®); in rt61pci_config_erp()
619 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); in rt61pci_config_erp()
620 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); in rt61pci_config_erp()
621 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); in rt61pci_config_erp()
622 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg); in rt61pci_config_erp()
713 u32 reg; in rt61pci_config_antenna_2529_rx() local
715 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); in rt61pci_config_antenna_2529_rx()
717 rt2x00_set_field32(®, MAC_CSR13_DIR4, 0); in rt61pci_config_antenna_2529_rx()
718 rt2x00_set_field32(®, MAC_CSR13_VAL4, p1); in rt61pci_config_antenna_2529_rx()
720 rt2x00_set_field32(®, MAC_CSR13_DIR3, 0); in rt61pci_config_antenna_2529_rx()
721 rt2x00_set_field32(®, MAC_CSR13_VAL3, !p2); in rt61pci_config_antenna_2529_rx()
723 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_config_antenna_2529_rx()
802 u32 reg; in rt61pci_config_ant() local
822 rt2x00mmio_register_read(rt2x00dev, PHY_CSR0, ®); in rt61pci_config_ant()
824 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, in rt61pci_config_ant()
826 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, in rt61pci_config_ant()
829 rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg); in rt61pci_config_ant()
927 u32 reg; in rt61pci_config_retry_limit() local
929 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, ®); in rt61pci_config_retry_limit()
930 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); in rt61pci_config_retry_limit()
931 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); in rt61pci_config_retry_limit()
932 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); in rt61pci_config_retry_limit()
933 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, in rt61pci_config_retry_limit()
935 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, in rt61pci_config_retry_limit()
937 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_retry_limit()
946 u32 reg; in rt61pci_config_ps() local
949 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, ®); in rt61pci_config_ps()
950 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, in rt61pci_config_ps()
952 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, in rt61pci_config_ps()
954 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); in rt61pci_config_ps()
957 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); in rt61pci_config_ps()
958 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
960 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); in rt61pci_config_ps()
961 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
970 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, ®); in rt61pci_config_ps()
971 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); in rt61pci_config_ps()
972 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); in rt61pci_config_ps()
973 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); in rt61pci_config_ps()
974 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); in rt61pci_config_ps()
975 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
1011 u32 reg; in rt61pci_link_stats() local
1016 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, ®); in rt61pci_link_stats()
1017 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); in rt61pci_link_stats()
1022 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, ®); in rt61pci_link_stats()
1023 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); in rt61pci_link_stats()
1137 u32 reg; in rt61pci_start_queue() local
1141 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_start_queue()
1142 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); in rt61pci_start_queue()
1143 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_start_queue()
1146 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_start_queue()
1147 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); in rt61pci_start_queue()
1148 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); in rt61pci_start_queue()
1149 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); in rt61pci_start_queue()
1150 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_start_queue()
1160 u32 reg; in rt61pci_kick_queue() local
1164 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1165 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, 1); in rt61pci_kick_queue()
1166 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1169 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1170 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, 1); in rt61pci_kick_queue()
1171 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1174 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1175 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, 1); in rt61pci_kick_queue()
1176 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1179 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1180 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, 1); in rt61pci_kick_queue()
1181 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1191 u32 reg; in rt61pci_stop_queue() local
1195 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1196 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1); in rt61pci_stop_queue()
1197 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1200 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1201 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1); in rt61pci_stop_queue()
1202 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1205 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1206 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1); in rt61pci_stop_queue()
1207 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1210 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1211 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1); in rt61pci_stop_queue()
1212 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1215 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_stop_queue()
1216 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1); in rt61pci_stop_queue()
1217 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_stop_queue()
1220 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_stop_queue()
1221 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); in rt61pci_stop_queue()
1222 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); in rt61pci_stop_queue()
1223 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_stop_queue()
1224 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_stop_queue()
1296 u32 reg; in rt61pci_load_firmware() local
1302 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, ®); in rt61pci_load_firmware()
1303 if (reg) in rt61pci_load_firmware()
1308 if (!reg) { in rt61pci_load_firmware()
1316 reg = 0; in rt61pci_load_firmware()
1317 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); in rt61pci_load_firmware()
1318 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1326 reg = 0; in rt61pci_load_firmware()
1327 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); in rt61pci_load_firmware()
1328 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1); in rt61pci_load_firmware()
1329 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1334 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0); in rt61pci_load_firmware()
1335 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1337 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0); in rt61pci_load_firmware()
1338 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1341 rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR, ®); in rt61pci_load_firmware()
1342 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY)) in rt61pci_load_firmware()
1360 reg = 0; in rt61pci_load_firmware()
1361 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); in rt61pci_load_firmware()
1362 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); in rt61pci_load_firmware()
1363 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1365 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_load_firmware()
1366 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); in rt61pci_load_firmware()
1367 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); in rt61pci_load_firmware()
1368 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1370 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_load_firmware()
1371 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); in rt61pci_load_firmware()
1372 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1423 u32 reg; in rt61pci_init_queues() local
1428 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0, ®); in rt61pci_init_queues()
1429 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE, in rt61pci_init_queues()
1431 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE, in rt61pci_init_queues()
1433 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE, in rt61pci_init_queues()
1435 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE, in rt61pci_init_queues()
1437 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg); in rt61pci_init_queues()
1439 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1, ®); in rt61pci_init_queues()
1440 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE, in rt61pci_init_queues()
1442 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg); in rt61pci_init_queues()
1445 rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR, ®); in rt61pci_init_queues()
1446 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1448 rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg); in rt61pci_init_queues()
1451 rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR, ®); in rt61pci_init_queues()
1452 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1454 rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg); in rt61pci_init_queues()
1457 rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR, ®); in rt61pci_init_queues()
1458 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1460 rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg); in rt61pci_init_queues()
1463 rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR, ®); in rt61pci_init_queues()
1464 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1466 rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg); in rt61pci_init_queues()
1468 rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR, ®); in rt61pci_init_queues()
1469 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); in rt61pci_init_queues()
1470 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE, in rt61pci_init_queues()
1472 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); in rt61pci_init_queues()
1473 rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg); in rt61pci_init_queues()
1476 rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR, ®); in rt61pci_init_queues()
1477 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1479 rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg); in rt61pci_init_queues()
1481 rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR, ®); in rt61pci_init_queues()
1482 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2); in rt61pci_init_queues()
1483 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2); in rt61pci_init_queues()
1484 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2); in rt61pci_init_queues()
1485 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2); in rt61pci_init_queues()
1486 rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); in rt61pci_init_queues()
1488 rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®); in rt61pci_init_queues()
1489 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); in rt61pci_init_queues()
1490 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); in rt61pci_init_queues()
1491 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); in rt61pci_init_queues()
1492 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); in rt61pci_init_queues()
1493 rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); in rt61pci_init_queues()
1495 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, ®); in rt61pci_init_queues()
1496 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1); in rt61pci_init_queues()
1497 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_init_queues()
1504 u32 reg; in rt61pci_init_registers() local
1506 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_init_registers()
1507 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); in rt61pci_init_registers()
1508 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); in rt61pci_init_registers()
1509 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); in rt61pci_init_registers()
1510 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_init_registers()
1512 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1, ®); in rt61pci_init_registers()
1513 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ in rt61pci_init_registers()
1514 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); in rt61pci_init_registers()
1515 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ in rt61pci_init_registers()
1516 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); in rt61pci_init_registers()
1517 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ in rt61pci_init_registers()
1518 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); in rt61pci_init_registers()
1519 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ in rt61pci_init_registers()
1520 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); in rt61pci_init_registers()
1521 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg); in rt61pci_init_registers()
1526 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2, ®); in rt61pci_init_registers()
1527 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); in rt61pci_init_registers()
1528 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); in rt61pci_init_registers()
1529 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); in rt61pci_init_registers()
1530 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); in rt61pci_init_registers()
1531 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); in rt61pci_init_registers()
1532 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); in rt61pci_init_registers()
1533 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); in rt61pci_init_registers()
1534 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); in rt61pci_init_registers()
1535 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg); in rt61pci_init_registers()
1540 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3, ®); in rt61pci_init_registers()
1541 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); in rt61pci_init_registers()
1542 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); in rt61pci_init_registers()
1543 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); in rt61pci_init_registers()
1544 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); in rt61pci_init_registers()
1545 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); in rt61pci_init_registers()
1546 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); in rt61pci_init_registers()
1547 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg); in rt61pci_init_registers()
1549 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7, ®); in rt61pci_init_registers()
1550 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); in rt61pci_init_registers()
1551 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); in rt61pci_init_registers()
1552 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); in rt61pci_init_registers()
1553 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); in rt61pci_init_registers()
1554 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg); in rt61pci_init_registers()
1556 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8, ®); in rt61pci_init_registers()
1557 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); in rt61pci_init_registers()
1558 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); in rt61pci_init_registers()
1559 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); in rt61pci_init_registers()
1560 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); in rt61pci_init_registers()
1561 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg); in rt61pci_init_registers()
1563 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_init_registers()
1564 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); in rt61pci_init_registers()
1565 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); in rt61pci_init_registers()
1566 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); in rt61pci_init_registers()
1567 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); in rt61pci_init_registers()
1568 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_init_registers()
1569 rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); in rt61pci_init_registers()
1570 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_init_registers()
1576 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, ®); in rt61pci_init_registers()
1577 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); in rt61pci_init_registers()
1578 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_init_registers()
1622 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, ®); in rt61pci_init_registers()
1623 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, ®); in rt61pci_init_registers()
1624 rt2x00mmio_register_read(rt2x00dev, STA_CSR2, ®); in rt61pci_init_registers()
1629 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_init_registers()
1630 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); in rt61pci_init_registers()
1631 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); in rt61pci_init_registers()
1632 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1634 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_init_registers()
1635 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); in rt61pci_init_registers()
1636 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); in rt61pci_init_registers()
1637 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1639 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_init_registers()
1640 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); in rt61pci_init_registers()
1641 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1717 u32 reg; in rt61pci_toggle_irq() local
1725 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); in rt61pci_toggle_irq()
1726 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1728 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®); in rt61pci_toggle_irq()
1729 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1738 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt61pci_toggle_irq()
1739 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask); in rt61pci_toggle_irq()
1740 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask); in rt61pci_toggle_irq()
1741 rt2x00_set_field32(®, INT_MASK_CSR_BEACON_DONE, mask); in rt61pci_toggle_irq()
1742 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask); in rt61pci_toggle_irq()
1743 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); in rt61pci_toggle_irq()
1744 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1746 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); in rt61pci_toggle_irq()
1747 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask); in rt61pci_toggle_irq()
1748 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask); in rt61pci_toggle_irq()
1749 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask); in rt61pci_toggle_irq()
1750 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask); in rt61pci_toggle_irq()
1751 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask); in rt61pci_toggle_irq()
1752 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask); in rt61pci_toggle_irq()
1753 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask); in rt61pci_toggle_irq()
1754 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask); in rt61pci_toggle_irq()
1755 rt2x00_set_field32(®, MCU_INT_MASK_CSR_TWAKEUP, mask); in rt61pci_toggle_irq()
1756 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1773 u32 reg; in rt61pci_enable_radio() local
1786 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, ®); in rt61pci_enable_radio()
1787 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1); in rt61pci_enable_radio()
1788 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_enable_radio()
1803 u32 reg, reg2; in rt61pci_set_state() local
1809 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, ®); in rt61pci_set_state()
1810 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); in rt61pci_set_state()
1811 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); in rt61pci_set_state()
1812 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1824 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1973 u32 orig_reg, reg; in rt61pci_write_beacon() local
1979 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_write_beacon()
1980 orig_reg = reg; in rt61pci_write_beacon()
1981 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_write_beacon()
1982 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
2021 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); in rt61pci_write_beacon()
2022 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
2034 u32 orig_reg, reg; in rt61pci_clear_beacon() local
2041 reg = orig_reg; in rt61pci_clear_beacon()
2042 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_clear_beacon()
2043 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_clear_beacon()
2161 u32 reg; in rt61pci_txdone() local
2176 rt2x00mmio_register_read(rt2x00dev, STA_CSR4, ®); in rt61pci_txdone()
2177 if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) in rt61pci_txdone()
2184 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); in rt61pci_txdone()
2193 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE); in rt61pci_txdone()
2221 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) { in rt61pci_txdone()
2231 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); in rt61pci_txdone()
2254 u32 reg; in rt61pci_enable_interrupt() local
2262 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt61pci_enable_interrupt()
2263 rt2x00_set_field32(®, irq_field, 0); in rt61pci_enable_interrupt()
2264 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_enable_interrupt()
2272 u32 reg; in rt61pci_enable_mcu_interrupt() local
2280 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); in rt61pci_enable_mcu_interrupt()
2281 rt2x00_set_field32(®, irq_field, 0); in rt61pci_enable_mcu_interrupt()
2282 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_enable_mcu_interrupt()
2326 u32 reg, mask; in rt61pci_interrupt() local
2335 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); in rt61pci_interrupt()
2336 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_interrupt()
2338 if (!reg && !reg_mcu) in rt61pci_interrupt()
2347 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE)) in rt61pci_interrupt()
2350 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE)) in rt61pci_interrupt()
2353 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE)) in rt61pci_interrupt()
2364 mask = reg; in rt61pci_interrupt()
2373 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt61pci_interrupt()
2374 reg |= mask; in rt61pci_interrupt()
2375 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_interrupt()
2377 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); in rt61pci_interrupt()
2378 reg |= mask_mcu; in rt61pci_interrupt()
2379 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_interrupt()
2392 u32 reg; in rt61pci_validate_eeprom() local
2397 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); in rt61pci_validate_eeprom()
2402 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ? in rt61pci_validate_eeprom()
2502 u32 reg; in rt61pci_init_eeprom() local
2515 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, ®); in rt61pci_init_eeprom()
2516 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), in rt61pci_init_eeprom()
2517 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); in rt61pci_init_eeprom()
2835 u32 reg; in rt61pci_probe_hw() local
2857 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); in rt61pci_probe_hw()
2858 rt2x00_set_field32(®, MAC_CSR13_DIR5, 1); in rt61pci_probe_hw()
2859 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_probe_hw()
2902 u32 reg; in rt61pci_conf_tx() local
2929 rt2x00mmio_register_read(rt2x00dev, offset, ®); in rt61pci_conf_tx()
2930 rt2x00_set_field32(®, field, queue->txop); in rt61pci_conf_tx()
2931 rt2x00mmio_register_write(rt2x00dev, offset, reg); in rt61pci_conf_tx()
2937 rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR, ®); in rt61pci_conf_tx()
2938 rt2x00_set_field32(®, field, queue->aifs); in rt61pci_conf_tx()
2939 rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg); in rt61pci_conf_tx()
2941 rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR, ®); in rt61pci_conf_tx()
2942 rt2x00_set_field32(®, field, queue->cw_min); in rt61pci_conf_tx()
2943 rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg); in rt61pci_conf_tx()
2945 rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR, ®); in rt61pci_conf_tx()
2946 rt2x00_set_field32(®, field, queue->cw_max); in rt61pci_conf_tx()
2947 rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg); in rt61pci_conf_tx()
2956 u32 reg; in rt61pci_get_tsf() local
2958 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13, ®); in rt61pci_get_tsf()
2959 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; in rt61pci_get_tsf()
2960 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12, ®); in rt61pci_get_tsf()
2961 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); in rt61pci_get_tsf()