Lines Matching refs:BIT
18 #define SYS_ISO_MD2PP BIT(0)
19 #define SYS_ISO_ANALOG_IPS BIT(5)
20 #define SYS_ISO_DIOR BIT(9)
21 #define SYS_ISO_PWC_EV25V BIT(14)
22 #define SYS_ISO_PWC_EV12V BIT(15)
25 #define SYS_FUNC_BBRSTB BIT(0)
26 #define SYS_FUNC_BB_GLB_RSTN BIT(1)
27 #define SYS_FUNC_USBA BIT(2)
28 #define SYS_FUNC_UPLL BIT(3)
29 #define SYS_FUNC_USBD BIT(4)
30 #define SYS_FUNC_DIO_PCIE BIT(5)
31 #define SYS_FUNC_PCIEA BIT(6)
32 #define SYS_FUNC_PPLL BIT(7)
33 #define SYS_FUNC_PCIED BIT(8)
34 #define SYS_FUNC_DIOE BIT(9)
35 #define SYS_FUNC_CPU_ENABLE BIT(10)
36 #define SYS_FUNC_DCORE BIT(11)
37 #define SYS_FUNC_ELDR BIT(12)
38 #define SYS_FUNC_DIO_RF BIT(13)
39 #define SYS_FUNC_HWPDN BIT(14)
40 #define SYS_FUNC_MREGEN BIT(15)
43 #define APS_FSMCO_PFM_ALDN BIT(1)
44 #define APS_FSMCO_PFM_WOWL BIT(3)
45 #define APS_FSMCO_ENABLE_POWERDOWN BIT(4)
46 #define APS_FSMCO_MAC_ENABLE BIT(8)
47 #define APS_FSMCO_MAC_OFF BIT(9)
48 #define APS_FSMCO_SW_LPS BIT(10)
49 #define APS_FSMCO_HW_SUSPEND BIT(11)
50 #define APS_FSMCO_PCIE BIT(12)
51 #define APS_FSMCO_HW_POWERDOWN BIT(15)
52 #define APS_FSMCO_WLON_RESET BIT(16)
55 #define SYS_CLK_ANAD16V_ENABLE BIT(0)
56 #define SYS_CLK_ANA8M BIT(1)
57 #define SYS_CLK_MACSLP BIT(4)
58 #define SYS_CLK_LOADER_ENABLE BIT(5)
59 #define SYS_CLK_80M_SSC_DISABLE BIT(7)
60 #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8)
61 #define SYS_CLK_PHY_SSC_RSTB BIT(9)
62 #define SYS_CLK_SEC_CLK_ENABLE BIT(10)
63 #define SYS_CLK_MAC_CLK_ENABLE BIT(11)
64 #define SYS_CLK_ENABLE BIT(12)
65 #define SYS_CLK_RING_CLK_ENABLE BIT(13)
68 #define EEPROM_BOOT BIT(4)
69 #define EEPROM_ENABLE BIT(5)
73 #define AFE_MISC_WL_XTAL_CTRL BIT(6)
81 #define RF_ENABLE BIT(0)
82 #define RF_RSTB BIT(1)
83 #define RF_SDMRSTB BIT(2)
86 #define LDOA15_ENABLE BIT(0)
87 #define LDOA15_STANDBY BIT(1)
88 #define LDOA15_OBUF BIT(2)
89 #define LDOA15_REG_VOS BIT(3)
93 #define LDOV12D_ENABLE BIT(0)
94 #define LDOV12D_STANDBY BIT(1)
100 #define LPLDO_HSM BIT(2)
101 #define LPLDO_LSM_DIS BIT(3)
104 #define AFE_XTAL_ENABLE BIT(0)
105 #define AFE_XTAL_B_SELECT BIT(1)
106 #define AFE_XTAL_GATE_USB BIT(8)
107 #define AFE_XTAL_GATE_AFE BIT(11)
108 #define AFE_XTAL_RF_GATE BIT(14)
109 #define AFE_XTAL_GATE_DIG BIT(17)
110 #define AFE_XTAL_BT_GATE BIT(20)
116 #define AFE_PLL_ENABLE BIT(0)
117 #define AFE_PLL_320_ENABLE BIT(1)
118 #define APE_PLL_FREF_SELECT BIT(2)
119 #define AFE_PLL_EDGE_SELECT BIT(3)
120 #define AFE_PLL_WDOGB BIT(4)
121 #define AFE_PLL_LPF_ENABLE BIT(5)
127 #define EFUSE_TRPT BIT(7)
129 #define EFUSE_CELL_SEL (BIT(8) | BIT(9))
130 #define EFUSE_LDOE25_ENABLE BIT(31)
141 #define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11)
150 #define GPIO_INTM_EDGE_TRIG_IRQ BIT(9)
153 #define LEDCFG0_DPDT_SELECT BIT(23)
156 #define LEDCFG2_DPDT_SELECT BIT(7)
167 #define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1)
168 #define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9)
172 #define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0)
177 #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW
179 #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity
181 #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */
183 #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW
185 #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW
187 #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity
189 #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */
190 #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS
192 #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW
194 #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity
196 #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */
202 #define MCU_FW_DL_ENABLE BIT(0)
203 #define MCU_FW_DL_READY BIT(1)
204 #define MCU_FW_DL_CSUM_REPORT BIT(2)
205 #define MCU_MAC_INIT_READY BIT(3)
206 #define MCU_BB_INIT_READY BIT(4)
207 #define MCU_RF_INIT_READY BIT(5)
208 #define MCU_WINT_INIT_READY BIT(6)
209 #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */
210 #define MCU_CP_RESET BIT(23)
219 #define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit
221 #define IMR0_PSTIMEOUT BIT(29) /* Power Save Time Out Int */
222 #define IMR0_GTINT4 BIT(28) /* Set when GTIMER4 expires */
223 #define IMR0_GTINT3 BIT(27) /* Set when GTIMER3 expires */
224 #define IMR0_TBDER BIT(26) /* Transmit Beacon0 Error */
225 #define IMR0_TBDOK BIT(25) /* Transmit Beacon0 OK */
226 #define IMR0_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle
228 #define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */
229 #define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */
230 #define IMR0_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR &
232 #define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt
234 #define IMR0_ATIMEND BIT(12) /* CTWidnow End or
236 #define IMR0_HISR1_IND_INT BIT(11) /* HISR1 Indicator
238 #define IMR0_C2HCMD BIT(10) /* CPU to Host Command INT
240 #define IMR0_CPWM2 BIT(9) /* CPU power Mode exchange INT
242 #define IMR0_CPWM BIT(8) /* CPU power Mode exchange INT
244 #define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */
245 #define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */
246 #define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */
247 #define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */
248 #define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */
249 #define IMR0_VODOK BIT(2) /* AC_VO DMA OK */
250 #define IMR0_RDU BIT(1) /* Rx Descriptor Unavailable */
251 #define IMR0_ROK BIT(0) /* Receive DMA OK */
254 #define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */
255 #define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */
256 #define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */
257 #define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */
258 #define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */
259 #define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */
260 #define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */
261 #define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */
262 #define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */
263 #define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */
264 #define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */
265 #define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */
266 #define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */
267 #define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */
268 #define IMR1_ATIMEND_E BIT(13) /* ATIM Window End Extension
270 #define IMR1_TXERR BIT(11) /* Tx Error Flag Int Status,
272 #define IMR1_RXERR BIT(10) /* Rx Error Flag Int Status,
274 #define IMR1_TXFOVW BIT(9) /* Transmit FIFO Overflow */
275 #define IMR1_RXFOVW BIT(8) /* Receive FIFO Overflow */
289 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23))
290 #define HPON_FSM_BONDING_1T2R BIT(22)
292 #define SYS_CFG_XCLK_VLD BIT(0)
293 #define SYS_CFG_ACLK_VLD BIT(1)
294 #define SYS_CFG_UCLK_VLD BIT(2)
295 #define SYS_CFG_PCLK_VLD BIT(3)
296 #define SYS_CFG_PCIRSTB BIT(4)
297 #define SYS_CFG_V15_VLD BIT(5)
298 #define SYS_CFG_TRP_B15V_EN BIT(7)
299 #define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */
300 #define SYS_CFG_SIC_IDLE BIT(8)
301 #define SYS_CFG_BD_MAC2 BIT(9)
302 #define SYS_CFG_BD_MAC1 BIT(10)
303 #define SYS_CFG_IC_MACPHY_MODE BIT(11)
304 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
305 #define SYS_CFG_BT_FUNC BIT(16)
306 #define SYS_CFG_VENDOR_ID BIT(19)
307 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19))
309 #define SYS_CFG_VENDOR_ID_SMIC BIT(18)
310 #define SYS_CFG_VENDOR_ID_UMC BIT(19)
311 #define SYS_CFG_PAD_HWPD_IDN BIT(22)
312 #define SYS_CFG_TRP_VAUX_EN BIT(23)
313 #define SYS_CFG_TRP_BT_EN BIT(24)
314 #define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */
315 #define SYS_CFG_BD_PKG_SEL BIT(25)
316 #define SYS_CFG_BD_HCI_SEL BIT(26)
317 #define SYS_CFG_TYPE_ID BIT(27)
318 #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID,
320 #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode;
326 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1))
327 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3))
328 #define GPIO_HCI_SEL (BIT(4) | BIT(5))
329 #define GPIO_PKG_SEL_HCI BIT(6)
330 #define GPIO_FEN_GPS BIT(7)
331 #define GPIO_FEN_BT BIT(8)
332 #define GPIO_FEN_WL BIT(9)
333 #define GPIO_FEN_PCI BIT(10)
334 #define GPIO_FEN_USB BIT(11)
335 #define GPIO_BTRF_HWPDN_N BIT(12)
336 #define GPIO_WLRF_HWPDN_N BIT(13)
337 #define GPIO_PDN_BT_N BIT(14)
338 #define GPIO_PDN_GPS_N BIT(15)
339 #define GPIO_BT_CTL_HWPDN BIT(16)
340 #define GPIO_GPS_CTL_HWPDN BIT(17)
341 #define GPIO_PPHY_SUSB BIT(20)
342 #define GPIO_UPHY_SUSB BIT(21)
343 #define GPIO_PCI_SUSEN BIT(22)
344 #define GPIO_USB_SUSEN BIT(23)
345 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
351 #define CR_HCI_TXDMA_ENABLE BIT(0)
352 #define CR_HCI_RXDMA_ENABLE BIT(1)
353 #define CR_TXDMA_ENABLE BIT(2)
354 #define CR_RXDMA_ENABLE BIT(3)
355 #define CR_PROTOCOL_ENABLE BIT(4)
356 #define CR_SCHEDULE_ENABLE BIT(5)
357 #define CR_MAC_TX_ENABLE BIT(6)
358 #define CR_MAC_RX_ENABLE BIT(7)
359 #define CR_SW_BEACON_ENABLE BIT(8)
360 #define CR_SECURITY_ENABLE BIT(9)
361 #define CR_CALTIMER_ENABLE BIT(10)
381 #define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2)
447 #define RQPN_LOAD BIT(31)
452 #define TXDMA_OFFSET_DROP_DATA_EN BIT(9)
459 #define AUTO_LLT_INIT_LLT BIT(16)
469 #define RXDMA_USB_AGG_ENABLE BIT(31)
471 #define RXPKT_NUM_RXDMA_IDLE BIT(17)
472 #define RXPKT_NUM_RW_RELEASE_EN BIT(18)
501 #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7)
502 #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12)
527 #define RSR_1M BIT(0)
528 #define RSR_2M BIT(1)
529 #define RSR_5_5M BIT(2)
530 #define RSR_11M BIT(3)
531 #define RSR_6M BIT(4)
532 #define RSR_9M BIT(5)
533 #define RSR_12M BIT(6)
534 #define RSR_18M BIT(7)
535 #define RSR_24M BIT(8)
536 #define RSR_36M BIT(9)
537 #define RSR_48M BIT(10)
538 #define RSR_54M BIT(11)
539 #define RSR_MCS0 BIT(12)
540 #define RSR_MCS1 BIT(13)
541 #define RSR_MCS2 BIT(14)
542 #define RSR_MCS3 BIT(15)
543 #define RSR_MCS4 BIT(16)
544 #define RSR_MCS5 BIT(17)
545 #define RSR_MCS6 BIT(18)
546 #define RSR_MCS7 BIT(19)
547 #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */
548 #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */
551 #define RSR_ACK_SHORT_PREAMBLE BIT(23)
599 #define TX_REPORT_CTRL_TIMER_ENABLE BIT(1)
630 #define BEACON_ATIM BIT(0)
631 #define BEACON_CTRL_MBSSID BIT(1)
632 #define BEACON_CTRL_TX_BEACON_RPT BIT(2)
633 #define BEACON_FUNCTION_ENABLE BIT(3)
634 #define BEACON_DISABLE_TSF_UPDATE BIT(4)
638 #define DUAL_TSF_RESET_TSF0 BIT(0)
639 #define DUAL_TSF_RESET_TSF1 BIT(1)
640 #define DUAL_TSF_RESET_P2P BIT(4)
641 #define DUAL_TSF_TX_OK BIT(5)
666 #define ACM_HW_CTRL_BK BIT(0)
667 #define ACM_HW_CTRL_BE BIT(1)
668 #define ACM_HW_CTRL_VI BIT(2)
669 #define ACM_HW_CTRL_VO BIT(3)
686 #define APSD_CTRL_OFF BIT(6)
687 #define APSD_CTRL_OFF_STATUS BIT(7)
689 #define BW_OPMODE_20MHZ BIT(2)
690 #define BW_OPMODE_5G BIT(1)
691 #define BW_OPMODE_11J BIT(0)
697 #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */
698 #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */
699 #define RCR_ACCEPT_MCAST BIT(2)
700 #define RCR_ACCEPT_BCAST BIT(3)
701 #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match
703 #define RCR_ACCEPT_PM BIT(5) /* Accept power management
705 #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */
706 #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet
708 #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */
709 #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */
710 #define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use
712 #define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use
714 #define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use
716 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */
717 #define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet
719 #define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet
721 #define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/
722 #define RCR_MFBEN BIT(22)
723 #define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection
727 #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */
728 #define RCR_FORCE_ACK BIT(26)
729 #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */
730 #define RCR_APPEND_PHYSTAT BIT(28)
731 #define RCR_APPEND_ICV BIT(29)
732 #define RCR_APPEND_MIC BIT(30)
733 #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */
768 #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8))
770 #define WMAC_TRXPTCL_CTL_BW_40 BIT(7)
771 #define WMAC_TRXPTCL_CTL_BW_80 BIT(8)
775 #define CAM_CMD_POLLING BIT(31)
776 #define CAM_CMD_WRITE BIT(16)
779 #define CAM_WRITE_VALID BIT(15)
783 #define SEC_CFG_TX_USE_DEFKEY BIT(0)
784 #define SEC_CFG_RX_USE_DEFKEY BIT(1)
785 #define SEC_CFG_TX_SEC_ENABLE BIT(2)
786 #define SEC_CFG_RX_SEC_ENABLE BIT(3)
787 #define SEC_CFG_SKBYA2 BIT(4)
788 #define SEC_CFG_NO_SKMC BIT(5)
789 #define SEC_CFG_TXBC_USE_DEFKEY BIT(6)
790 #define SEC_CFG_RXBC_USE_DEFKEY BIT(7)
829 #define BT_CONTROL_BT_GRANT BIT(12)
834 #define FPGA_RF_MODE BIT(0)
835 #define FPGA_RF_MODE_JAPAN BIT(1)
836 #define FPGA_RF_MODE_CCK BIT(24)
837 #define FPGA_RF_MODE_OFDM BIT(25)
840 #define FPGA0_TX_INFO_OFDM_PATH_A BIT(0)
841 #define FPGA0_TX_INFO_OFDM_PATH_B BIT(1)
842 #define FPGA0_TX_INFO_OFDM_PATH_C BIT(2)
843 #define FPGA0_TX_INFO_OFDM_PATH_D BIT(3)
849 #define FPGA0_PS_LOWER_CHANNEL BIT(26)
850 #define FPGA0_PS_UPPER_CHANNEL BIT(27)
853 #define FPGA0_HSSI_PARM1_PI BIT(8)
861 #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9)
862 #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31)
883 #define FPGA0_INT_OE_ANTENNA_A BIT(8)
884 #define FPGA0_INT_OE_ANTENNA_B BIT(9)
897 #define FPGA0_RF_3WIRE_DATA BIT(0)
898 #define FPGA0_RF_3WIRE_CLOC BIT(1)
899 #define FPGA0_RF_3WIRE_LOAD BIT(2)
900 #define FPGA0_RF_3WIRE_RW BIT(3)
902 #define FPGA0_RF_RFENV BIT(4)
903 #define FPGA0_RF_TRSW BIT(5) /* Useless now */
904 #define FPGA0_RF_TRSWB BIT(6)
905 #define FPGA0_RF_ANTSW BIT(8)
906 #define FPGA0_RF_ANTSWB BIT(9)
907 #define FPGA0_RF_PAPE BIT(10)
908 #define FPGA0_RF_PAPE5G BIT(11)
917 #define FPGA0_RF_PARM_RFA_ENABLE BIT(1)
918 #define FPGA0_RF_PARM_RFB_ENABLE BIT(17)
919 #define FPGA0_RF_PARM_CLK_GATE BIT(31)
923 #define FPGA0_ANALOG2_20MHZ BIT(10)
947 #define CCK0_SIDEBAND BIT(4)
951 #define CCK0_AFE_RX_ANT_AB BIT(24)
953 #define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26))
960 #define OFDM_RF_PATH_RX_A BIT(0)
961 #define OFDM_RF_PATH_RX_B BIT(1)
962 #define OFDM_RF_PATH_RX_C BIT(2)
963 #define OFDM_RF_PATH_RX_D BIT(3)
965 #define OFDM_RF_PATH_TX_A BIT(4)
966 #define OFDM_RF_PATH_TX_B BIT(5)
967 #define OFDM_RF_PATH_TX_C BIT(6)
968 #define OFDM_RF_PATH_TX_D BIT(7)
980 #define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1)
1010 #define OFDM_LSTF_PRIME_CH_LOW BIT(10)
1011 #define OFDM_LSTF_PRIME_CH_HIGH BIT(11)
1014 #define OFDM_LSTF_CONTINUE_TX BIT(28)
1015 #define OFDM_LSTF_SINGLE_CARRIER BIT(29)
1016 #define OFDM_LSTF_SINGLE_TONE BIT(30)
1083 #define USB_HIMR_TIMEOUT2 BIT(31)
1084 #define USB_HIMR_TIMEOUT1 BIT(30)
1085 #define USB_HIMR_PSTIMEOUT BIT(29)
1086 #define USB_HIMR_GTINT4 BIT(28)
1087 #define USB_HIMR_GTINT3 BIT(27)
1088 #define USB_HIMR_TXBCNERR BIT(26)
1089 #define USB_HIMR_TXBCNOK BIT(25)
1090 #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24)
1091 #define USB_HIMR_BCNDMAINT3 BIT(23)
1092 #define USB_HIMR_BCNDMAINT2 BIT(22)
1093 #define USB_HIMR_BCNDMAINT1 BIT(21)
1094 #define USB_HIMR_BCNDMAINT0 BIT(20)
1095 #define USB_HIMR_BCNDOK3 BIT(19)
1096 #define USB_HIMR_BCNDOK2 BIT(18)
1097 #define USB_HIMR_BCNDOK1 BIT(17)
1098 #define USB_HIMR_BCNDOK0 BIT(16)
1099 #define USB_HIMR_HSISR_IND BIT(15)
1100 #define USB_HIMR_BCNDMAINT_E BIT(14)
1102 #define USB_HIMR_CTW_END BIT(12)
1104 #define USB_HIMR_C2HCMD BIT(10)
1105 #define USB_HIMR_CPWM2 BIT(9)
1106 #define USB_HIMR_CPWM BIT(8)
1107 #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK
1109 #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK
1111 #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */
1112 #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */
1113 #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */
1114 #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */
1115 #define USB_HIMR_RDU BIT(1) /* Receive Descriptor
1117 #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */
1120 #define USB_SPEC_USB_AGG_ENABLE BIT(3) /* Enable USB aggregation */
1121 #define USB_SPEC_INT_BULK_SELECT BIT(4) /* Use interrupt endpoint to
1171 #define MODE_AG_CHANNEL_20MHZ BIT(10)
1172 #define MODE_AG_BW_MASK (BIT(10) | BIT(11))
1173 #define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11))
1174 #define MODE_AG_BW_40MHZ_8723B BIT(10)