Lines Matching refs:BIT
389 #define CMDEEPROM_EN BIT(5)
390 #define CMDEEPROM_SEL BIT(4)
391 #define CMD9346CR_9356SEL BIT(4)
396 #define GPIOSEL_ENBT BIT(5)
404 #define HSIMR_GPIO12_0_INT_EN BIT(0)
405 #define HSIMR_SPS_OCP_INT_EN BIT(5)
406 #define HSIMR_RON_INT_EN BIT(6)
407 #define HSIMR_PDN_INT_EN BIT(7)
408 #define HSIMR_GPIO9_INT_EN BIT(25)
411 #define HSISR_GPIO12_0_INT BIT(0)
412 #define HSISR_SPS_OCP_INT BIT(5)
413 #define HSISR_RON_INT_EN BIT(6)
414 #define HSISR_PDNINT BIT(7)
415 #define HSISR_GPIO9_INT BIT(25)
428 #define RRSR_1M BIT(0)
429 #define RRSR_2M BIT(1)
430 #define RRSR_5_5M BIT(2)
431 #define RRSR_11M BIT(3)
432 #define RRSR_6M BIT(4)
433 #define RRSR_9M BIT(5)
434 #define RRSR_12M BIT(6)
435 #define RRSR_18M BIT(7)
436 #define RRSR_24M BIT(8)
437 #define RRSR_36M BIT(9)
438 #define RRSR_48M BIT(10)
439 #define RRSR_54M BIT(11)
440 #define RRSR_MCS0 BIT(12)
441 #define RRSR_MCS1 BIT(13)
442 #define RRSR_MCS2 BIT(14)
443 #define RRSR_MCS3 BIT(15)
444 #define RRSR_MCS4 BIT(16)
445 #define RRSR_MCS5 BIT(17)
446 #define RRSR_MCS6 BIT(18)
447 #define RRSR_MCS7 BIT(19)
448 #define BRSR_ACKSHORTPMB BIT(23)
479 #define RATE_1M BIT(0)
480 #define RATE_2M BIT(1)
481 #define RATE_5_5M BIT(2)
482 #define RATE_11M BIT(3)
483 #define RATE_6M BIT(4)
484 #define RATE_9M BIT(5)
485 #define RATE_12M BIT(6)
486 #define RATE_18M BIT(7)
487 #define RATE_24M BIT(8)
488 #define RATE_36M BIT(9)
489 #define RATE_48M BIT(10)
490 #define RATE_54M BIT(11)
491 #define RATE_MCS0 BIT(12)
492 #define RATE_MCS1 BIT(13)
493 #define RATE_MCS2 BIT(14)
494 #define RATE_MCS3 BIT(15)
495 #define RATE_MCS4 BIT(16)
496 #define RATE_MCS5 BIT(17)
497 #define RATE_MCS6 BIT(18)
498 #define RATE_MCS7 BIT(19)
499 #define RATE_MCS8 BIT(20)
500 #define RATE_MCS9 BIT(21)
501 #define RATE_MCS10 BIT(22)
502 #define RATE_MCS11 BIT(23)
503 #define RATE_MCS12 BIT(24)
504 #define RATE_MCS13 BIT(25)
505 #define RATE_MCS14 BIT(26)
506 #define RATE_MCS15 BIT(27)
518 #define BW_OPMODE_20MHZ BIT(2)
519 #define BW_OPMODE_5G BIT(1)
520 #define BW_OPMODE_11J BIT(0)
522 #define CAM_VALID BIT(15)
524 #define CAM_USEDK BIT(5)
535 #define CAM_WRITE BIT(16)
537 #define CAM_POLLINIG BIT(31)
543 #define WOW_PMEN BIT(0)
544 #define WOW_WOMEN BIT(1)
545 #define WOW_MAGIC BIT(2)
546 #define WOW_UWF BIT(3)
554 #define IMR_TXCCK BIT(30) /* TXRPT interrupt when
557 #define IMR_PSTIMEOUT BIT(29) /* Power Save Time Out Interrupt */
558 #define IMR_GTINT4 BIT(28) /* When GTIMER4 expires,
561 #define IMR_GTINT3 BIT(27) /* When GTIMER3 expires,
564 #define IMR_TBDER BIT(26) /* Transmit Beacon0 Error */
565 #define IMR_TBDOK BIT(25) /* Transmit Beacon0 OK */
566 #define IMR_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle
569 #define IMR_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */
570 #define IMR_BCNDOK0 BIT(16) /* Beacon Queue DMA OK0 */
571 #define IMR_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & HSISR is
574 #define IMR_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt
577 #define IMR_ATIMEND BIT(12) /* CTWidnow End or ATIM Window End */
578 #define IMR_HISR1_IND_INT BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is
581 #define IMR_C2HCMD BIT(10) /* CPU to Host Command INT Status,
584 #define IMR_CPWM2 BIT(9) /* CPU power Mode exchange INT Status,
587 #define IMR_CPWM BIT(8) /* CPU power Mode exchange INT Status,
590 #define IMR_HIGHDOK BIT(7) /* High Queue DMA OK */
591 #define IMR_MGNTDOK BIT(6) /* Management Queue DMA OK */
592 #define IMR_BKDOK BIT(5) /* AC_BK DMA OK */
593 #define IMR_BEDOK BIT(4) /* AC_BE DMA OK */
594 #define IMR_VIDOK BIT(3) /* AC_VI DMA OK */
595 #define IMR_VODOK BIT(2) /* AC_VO DMA OK */
596 #define IMR_RDU BIT(1) /* Rx Descriptor Unavailable */
597 #define IMR_ROK BIT(0) /* Receive DMA OK */
600 #define IMR_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */
601 #define IMR_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */
602 #define IMR_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */
603 #define IMR_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */
604 #define IMR_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */
605 #define IMR_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */
606 #define IMR_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */
607 #define IMR_BCNDOK7 BIT(20) /* Beacon Queue DMA OK Interrup 7 */
608 #define IMR_BCNDOK6 BIT(19) /* Beacon Queue DMA OK Interrup 6 */
609 #define IMR_BCNDOK5 BIT(18) /* Beacon Queue DMA OK Interrup 5 */
610 #define IMR_BCNDOK4 BIT(17) /* Beacon Queue DMA OK Interrup 4 */
611 #define IMR_BCNDOK3 BIT(16) /* Beacon Queue DMA OK Interrup 3 */
612 #define IMR_BCNDOK2 BIT(15) /* Beacon Queue DMA OK Interrup 2 */
613 #define IMR_BCNDOK1 BIT(14) /* Beacon Queue DMA OK Interrup 1 */
614 #define IMR_ATIMEND_E BIT(13) /* ATIM Window End Extension for Win7 */
615 #define IMR_TXERR BIT(11) /* Tx Error Flag Interrupt Status,
618 #define IMR_RXERR BIT(10) /* Rx Error Flag INT Status,
621 #define IMR_TXFOVW BIT(9) /* Transmit FIFO Overflow */
622 #define IMR_RXFOVW BIT(8) /* Receive FIFO Overflow */
712 #define STOPBECON BIT(6)
713 #define STOPHIGHT BIT(5)
714 #define STOPMGT BIT(4)
715 #define STOPVO BIT(3)
716 #define STOPVI BIT(2)
717 #define STOPBE BIT(1)
718 #define STOPBK BIT(0)
720 #define RCR_APPFCS BIT(31)
721 #define RCR_APP_MIC BIT(30)
722 #define RCR_APP_ICV BIT(29)
723 #define RCR_APP_PHYST_RXFF BIT(28)
724 #define RCR_APP_BA_SSN BIT(27)
725 #define RCR_ENMBID BIT(24)
726 #define RCR_LSIGEN BIT(23)
727 #define RCR_MFBEN BIT(22)
728 #define RCR_HTC_LOC_CTRL BIT(14)
729 #define RCR_AMF BIT(13)
730 #define RCR_ACF BIT(12)
731 #define RCR_ADF BIT(11)
732 #define RCR_AICV BIT(9)
733 #define RCR_ACRC32 BIT(8)
734 #define RCR_CBSSID_BCN BIT(7)
735 #define RCR_CBSSID_DATA BIT(6)
737 #define RCR_APWRMGT BIT(5)
738 #define RCR_ADD3 BIT(4)
739 #define RCR_AB BIT(3)
740 #define RCR_AM BIT(2)
741 #define RCR_APM BIT(1)
742 #define RCR_AAP BIT(0)
764 #define SW18_FPWM BIT(3)
766 #define ISO_MD2PP BIT(0)
767 #define ISO_UA2USB BIT(1)
768 #define ISO_UD2CORE BIT(2)
769 #define ISO_PA2PCIE BIT(3)
770 #define ISO_PD2CORE BIT(4)
771 #define ISO_IP2MAC BIT(5)
772 #define ISO_DIOP BIT(6)
773 #define ISO_DIOE BIT(7)
774 #define ISO_EB2CORE BIT(8)
775 #define ISO_DIOR BIT(9)
777 #define PWC_EV25V BIT(14)
778 #define PWC_EV12V BIT(15)
780 #define FEN_BBRSTB BIT(0)
781 #define FEN_BB_GLB_RSTN BIT(1)
782 #define FEN_USBA BIT(2)
783 #define FEN_UPLL BIT(3)
784 #define FEN_USBD BIT(4)
785 #define FEN_DIO_PCIE BIT(5)
786 #define FEN_PCIEA BIT(6)
787 #define FEN_PPLL BIT(7)
788 #define FEN_PCIED BIT(8)
789 #define FEN_DIOE BIT(9)
790 #define FEN_CPUEN BIT(10)
791 #define FEN_DCORE BIT(11)
792 #define FEN_ELDR BIT(12)
793 #define FEN_DIO_RF BIT(13)
794 #define FEN_HWPDN BIT(14)
795 #define FEN_MREGEN BIT(15)
797 #define PFM_LDALL BIT(0)
798 #define PFM_ALDN BIT(1)
799 #define PFM_LDKP BIT(2)
800 #define PFM_WOWL BIT(3)
801 #define ENPDN BIT(4)
802 #define PDN_PL BIT(5)
803 #define APFM_ONMAC BIT(8)
804 #define APFM_OFF BIT(9)
805 #define APFM_RSM BIT(10)
806 #define AFSM_HSUS BIT(11)
807 #define AFSM_PCIE BIT(12)
808 #define APDM_MAC BIT(13)
809 #define APDM_HOST BIT(14)
810 #define APDM_HPDN BIT(15)
811 #define RDY_MACON BIT(16)
812 #define SUS_HOST BIT(17)
813 #define ROP_ALD BIT(20)
814 #define ROP_PWR BIT(21)
815 #define ROP_SPS BIT(22)
816 #define SOP_MRST BIT(25)
817 #define SOP_FUSE BIT(26)
818 #define SOP_ABG BIT(27)
819 #define SOP_AMB BIT(28)
820 #define SOP_RCK BIT(29)
821 #define SOP_A8M BIT(30)
822 #define XOP_BTCK BIT(31)
824 #define ANAD16V_EN BIT(0)
825 #define ANA8M BIT(1)
826 #define MACSLP BIT(4)
827 #define LOADER_CLK_EN BIT(5)
828 #define _80M_SSC_DIS BIT(7)
829 #define _80M_SSC_EN_HO BIT(8)
830 #define PHY_SSC_RSTB BIT(9)
831 #define SEC_CLK_EN BIT(10)
832 #define MAC_CLK_EN BIT(11)
833 #define SYS_CLK_EN BIT(12)
834 #define RING_CLK_EN BIT(13)
836 #define BOOT_FROM_EEPROM BIT(4)
837 #define EEPROM_EN BIT(5)
839 #define AFE_BGEN BIT(0)
840 #define AFE_MBEN BIT(1)
841 #define MAC_ID_EN BIT(7)
843 #define WLOCK_ALL BIT(0)
844 #define WLOCK_00 BIT(1)
845 #define WLOCK_04 BIT(2)
846 #define WLOCK_08 BIT(3)
847 #define WLOCK_40 BIT(4)
848 #define R_DIS_PRST_0 BIT(5)
849 #define R_DIS_PRST_1 BIT(6)
850 #define LOCK_ALL_EN BIT(7)
852 #define RF_EN BIT(0)
853 #define RF_RSTB BIT(1)
854 #define RF_SDMRSTB BIT(2)
856 #define LDA15_EN BIT(0)
857 #define LDA15_STBY BIT(1)
858 #define LDA15_OBUF BIT(2)
859 #define LDA15_REG_VOS BIT(3)
862 #define LDV12_EN BIT(0)
863 #define LDV12_SDBY BIT(1)
864 #define LPLDO_HSM BIT(2)
865 #define LPLDO_LSM_DIS BIT(3)
868 #define XTAL_EN BIT(0)
869 #define XTAL_BSEL BIT(1)
872 #define XTAL_GATE_USB BIT(8)
874 #define XTAL_GATE_AFE BIT(11)
876 #define XTAL_RF_GATE BIT(14)
878 #define XTAL_GATE_DIG BIT(17)
880 #define XTAL_BT_GATE BIT(20)
884 #define CKDLY_AFE BIT(26)
885 #define CKDLY_USB BIT(27)
886 #define CKDLY_DIG BIT(28)
887 #define CKDLY_BT BIT(29)
889 #define APLL_EN BIT(0)
890 #define APLL_320_EN BIT(1)
891 #define APLL_FREF_SEL BIT(2)
892 #define APLL_EDGE_SEL BIT(3)
893 #define APLL_WDOGB BIT(4)
894 #define APLL_LPFEN BIT(5)
904 #define APLL_320EN BIT(14)
905 #define APLL_80EN BIT(15)
906 #define APLL_1MEN BIT(24)
908 #define ALD_EN BIT(18)
909 #define EF_PD BIT(19)
910 #define EF_FLAG BIT(31)
912 #define EF_TRPT BIT(7)
913 #define LDOE25_EN BIT(31)
915 #define RSM_EN BIT(0)
916 #define TIMER_EN BIT(4)
918 #define TRSW0EN BIT(2)
919 #define TRSW1EN BIT(3)
920 #define EROM_EN BIT(4)
921 #define ENBT BIT(5)
922 #define ENUART BIT(8)
923 #define UART_910 BIT(9)
924 #define ENPMAC BIT(10)
925 #define SIC_SWRST BIT(11)
926 #define ENSIC BIT(12)
927 #define SIC_23 BIT(13)
928 #define ENHDP BIT(14)
929 #define SIC_LBK BIT(15)
931 #define LED0PL BIT(4)
932 #define LED1PL BIT(12)
933 #define LED0DIS BIT(7)
935 #define MCUFWDL_EN BIT(0)
936 #define MCUFWDL_RDY BIT(1)
937 #define FWDL_CHKSUM_RPT BIT(2)
938 #define MACINI_RDY BIT(3)
939 #define BBINI_RDY BIT(4)
940 #define RFINI_RDY BIT(5)
941 #define WINTINI_RDY BIT(6)
942 #define CPRST BIT(23)
944 #define XCLK_VLD BIT(0)
945 #define ACLK_VLD BIT(1)
946 #define UCLK_VLD BIT(2)
947 #define PCLK_VLD BIT(3)
948 #define PCIRSTB BIT(4)
949 #define V15_VLD BIT(5)
950 #define TRP_B15V_EN BIT(7)
951 #define SIC_IDLE BIT(8)
952 #define BD_MAC2 BIT(9)
953 #define BD_MAC1 BIT(10)
954 #define IC_MACPHY_MODE BIT(11)
955 #define VENDOR_ID BIT(19)
956 #define PAD_HWPD_IDN BIT(22)
957 #define TRP_VAUX_EN BIT(23)
958 #define TRP_BT_EN BIT(24)
959 #define BD_PKG_SEL BIT(25)
960 #define BD_HCI_SEL BIT(26)
961 #define TYPE_ID BIT(27)
968 #define HCI_TXDMA_EN BIT(0)
969 #define HCI_RXDMA_EN BIT(1)
970 #define TXDMA_EN BIT(2)
971 #define RXDMA_EN BIT(3)
972 #define PROTOCOL_EN BIT(4)
973 #define SCHEDULE_EN BIT(5)
974 #define MACTXEN BIT(6)
975 #define MACRXEN BIT(7)
976 #define ENSWBCN BIT(8)
977 #define ENSEC BIT(9)
1007 #define RXDMA_ARBBW_EN BIT(0)
1008 #define RXSHFT_EN BIT(1)
1009 #define RXDMA_AGG_EN BIT(2)
1010 #define QS_VO_QUEUE BIT(8)
1011 #define QS_VI_QUEUE BIT(9)
1012 #define QS_BE_QUEUE BIT(10)
1013 #define QS_BK_QUEUE BIT(11)
1014 #define QS_MANAGER_QUEUE BIT(12)
1015 #define QS_HIGH_QUEUE BIT(13)
1017 #define HQSEL_VOQ BIT(0)
1018 #define HQSEL_VIQ BIT(1)
1019 #define HQSEL_BEQ BIT(2)
1020 #define HQSEL_BKQ BIT(3)
1021 #define HQSEL_MGTQ BIT(4)
1022 #define HQSEL_HIQ BIT(5)
1044 #define BB_WRITE_READ_MASK (BIT(31) | BIT(30))
1045 #define BB_WRITE_EN BIT(30)
1046 #define BB_READ_EN BIT(31)
1053 #define HPQ_PUBLIC_DIS BIT(24)
1054 #define LPQ_PUBLIC_DIS BIT(25)
1055 #define LD_RQPN BIT(31)
1057 #define BCN_VALID BIT(16)
1064 #define DROP_DATA_EN BIT(9)
1066 #define EN_AMPDU_RTY_NEW BIT(7)
1083 #define USE_SHORT_G1 BIT(20)
1138 #define DIS_EDCA_CNT_DWN BIT(11)
1140 #define EN_MBSSID BIT(1)
1141 #define EN_TXBCN_RPT BIT(2)
1142 #define EN_BCN_FUNCTION BIT(3)
1144 #define TSFTR_RST BIT(0)
1145 #define TSFTR1_RST BIT(1)
1147 #define STOP_BCNQ BIT(6)
1149 #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
1150 #define DIS_TSF_UDT0_TEST_CHIP BIT(5)
1152 #define ACMHW_HWEN BIT(0)
1153 #define ACMHW_BEQEN BIT(1)
1154 #define ACMHW_VIQEN BIT(2)
1155 #define ACMHW_VOQEN BIT(3)
1156 #define ACMHW_BEQSTATUS BIT(4)
1157 #define ACMHW_VIQSTATUS BIT(5)
1158 #define ACMHW_VOQSTATUS BIT(6)
1160 #define APSDOFF BIT(6)
1161 #define APSDOFF_STATUS BIT(7)
1163 #define BW_20MHZ BIT(2)
1169 #define TSFRST BIT(0)
1170 #define DIS_GCLK BIT(1)
1171 #define PAD_SEL BIT(2)
1172 #define PWR_ST BIT(6)
1173 #define PWRBIT_OW_EN BIT(7)
1174 #define ACRC BIT(8)
1175 #define CFENDFORM BIT(9)
1176 #define ICV BIT(10)
1178 #define AAP BIT(0)
1179 #define APM BIT(1)
1180 #define AM BIT(2)
1181 #define AB BIT(3)
1182 #define ADD3 BIT(4)
1183 #define APWRMGT BIT(5)
1184 #define CBSSID BIT(6)
1185 #define CBSSID_DATA BIT(6)
1186 #define CBSSID_BCN BIT(7)
1187 #define ACRC32 BIT(8)
1188 #define AICV BIT(9)
1189 #define ADF BIT(11)
1190 #define ACF BIT(12)
1191 #define AMF BIT(13)
1192 #define HTC_LOC_CTRL BIT(14)
1193 #define UC_DATA_EN BIT(16)
1194 #define BM_DATA_EN BIT(17)
1195 #define MFBEN BIT(22)
1196 #define LSIGEN BIT(23)
1197 #define ENMBID BIT(24)
1198 #define APP_BASSN BIT(27)
1199 #define APP_PHYSTS BIT(28)
1200 #define APP_ICV BIT(29)
1201 #define APP_MIC BIT(30)
1202 #define APP_FCS BIT(31)
1223 #define RXERR_RPT_RST BIT(27)
1226 #define SCR_TXUSEDK BIT(0)
1227 #define SCR_RXUSEDK BIT(1)
1228 #define SCR_TXENCENABLE BIT(2)
1229 #define SCR_RXDECENABLE BIT(3)
1230 #define SCR_SKBYA2 BIT(4)
1231 #define SCR_NOSKMC BIT(5)
1232 #define SCR_TXBCUSEDK BIT(6)
1233 #define SCR_RXBCUSEDK BIT(7)
1235 #define XCLK_VLD BIT(0)
1236 #define ACLK_VLD BIT(1)
1237 #define UCLK_VLD BIT(2)
1238 #define PCLK_VLD BIT(3)
1239 #define PCIRSTB BIT(4)
1240 #define V15_VLD BIT(5)
1241 #define TRP_B15V_EN BIT(7)
1242 #define SIC_IDLE BIT(8)
1243 #define BD_MAC2 BIT(9)
1244 #define BD_MAC1 BIT(10)
1245 #define IC_MACPHY_MODE BIT(11)
1246 #define BT_FUNC BIT(16)
1247 #define VENDOR_ID BIT(19)
1248 #define PAD_HWPD_IDN BIT(22)
1249 #define TRP_VAUX_EN BIT(23)
1250 #define TRP_BT_EN BIT(24)
1251 #define BD_PKG_SEL BIT(25)
1252 #define BD_HCI_SEL BIT(26)
1253 #define TYPE_ID BIT(27)
1257 #define USB_SPEED_MASK BIT(5)
1265 #define USB_AGG_EN BIT(3)
1282 #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
2275 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)
2276 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)
2277 #define HAL92C_WOL_DISASSOC_EVENT BIT(2)
2278 #define HAL92C_WOL_DEAUTH_EVENT BIT(3)
2279 #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4)
2281 #define WOL_REASON_PTK_UPDATE BIT(0)
2282 #define WOL_REASON_GTK_UPDATE BIT(1)
2283 #define WOL_REASON_DISASSOC BIT(2)
2284 #define WOL_REASON_DEAUTH BIT(3)
2285 #define WOL_REASON_FW_DISCONNECT BIT(4)
2292 #define WL_HWPDN_EN BIT(0) /* Enable GPIO[9] as WiFi HW PDn source*/
2293 #define WL_HWPDN_SL BIT(1) /* WiFi HW PDn polarity control*/