Lines Matching refs:wl
674 static int wl18xx_identify_chip(struct wl1271 *wl) in wl18xx_identify_chip() argument
678 switch (wl->chip.id) { in wl18xx_identify_chip()
681 wl->chip.id); in wl18xx_identify_chip()
682 wl->sr_fw_name = WL18XX_FW_NAME; in wl18xx_identify_chip()
684 wl->plt_fw_name = WL18XX_FW_NAME; in wl18xx_identify_chip()
685 wl->quirks |= WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN | in wl18xx_identify_chip()
692 wlcore_set_min_fw_ver(wl, WL18XX_CHIP_VER, in wl18xx_identify_chip()
700 wl->chip.id); in wl18xx_identify_chip()
705 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id); in wl18xx_identify_chip()
710 wl->fw_mem_block_size = 272; in wl18xx_identify_chip()
711 wl->fwlog_end = 0x40000000; in wl18xx_identify_chip()
713 wl->scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4; in wl18xx_identify_chip()
714 wl->scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5; in wl18xx_identify_chip()
715 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_PROBE_REQ_2_4_PERIODIC; in wl18xx_identify_chip()
716 wl->sched_scan_templ_id_5 = CMD_TEMPL_PROBE_REQ_5_PERIODIC; in wl18xx_identify_chip()
717 wl->max_channels_5 = WL18XX_MAX_CHANNELS_5GHZ; in wl18xx_identify_chip()
718 wl->ba_rx_session_count_max = WL18XX_RX_BA_MAX_SESSIONS; in wl18xx_identify_chip()
723 static int wl18xx_set_clk(struct wl1271 *wl) in wl18xx_set_clk() argument
728 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); in wl18xx_set_clk()
734 ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq); in wl18xx_set_clk()
744 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_N, in wl18xx_set_clk()
749 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_M, in wl18xx_set_clk()
755 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN, in wl18xx_set_clk()
760 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N, in wl18xx_set_clk()
765 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M, in wl18xx_set_clk()
772 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1, in wl18xx_set_clk()
779 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2, in wl18xx_set_clk()
786 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1, in wl18xx_set_clk()
793 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2, in wl18xx_set_clk()
797 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN, in wl18xx_set_clk()
802 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_SEL, in wl18xx_set_clk()
808 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL1); in wl18xx_set_clk()
815 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL2); in wl18xx_set_clk()
820 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN, in wl18xx_set_clk()
829 static int wl18xx_boot_soft_reset(struct wl1271 *wl) in wl18xx_boot_soft_reset() argument
834 ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0); in wl18xx_boot_soft_reset()
839 ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff); in wl18xx_boot_soft_reset()
845 static int wl18xx_pre_boot(struct wl1271 *wl) in wl18xx_pre_boot() argument
849 ret = wl18xx_set_clk(wl); in wl18xx_pre_boot()
854 ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); in wl18xx_pre_boot()
860 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); in wl18xx_pre_boot()
865 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); in wl18xx_pre_boot()
869 ret = wl18xx_boot_soft_reset(wl); in wl18xx_pre_boot()
875 static int wl18xx_pre_upload(struct wl1271 *wl) in wl18xx_pre_upload() argument
884 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); in wl18xx_pre_upload()
889 ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND); in wl18xx_pre_upload()
893 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp); in wl18xx_pre_upload()
899 ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp); in wl18xx_pre_upload()
910 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]); in wl18xx_pre_upload()
915 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1, in wl18xx_pre_upload()
921 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1, in wl18xx_pre_upload()
927 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1, in wl18xx_pre_upload()
932 ret = irq_get_trigger_type(wl->irq); in wl18xx_pre_upload()
935 ret = wlcore_set_partition(wl, in wl18xx_pre_upload()
936 &wl->ptable[PART_TOP_PRCM_ELP_SOC]); in wl18xx_pre_upload()
940 ret = wl18xx_top_reg_read(wl, TOP_FN0_CCCR_REG_32, &irq_invert); in wl18xx_pre_upload()
945 ret = wl18xx_top_reg_write(wl, TOP_FN0_CCCR_REG_32, irq_invert); in wl18xx_pre_upload()
949 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]); in wl18xx_pre_upload()
956 static int wl18xx_set_mac_and_phy(struct wl1271 *wl) in wl18xx_set_mac_and_phy() argument
958 struct wl18xx_priv *priv = wl->priv; in wl18xx_set_mac_and_phy()
968 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]); in wl18xx_set_mac_and_phy()
972 ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, params, in wl18xx_set_mac_and_phy()
980 static int wl18xx_enable_interrupts(struct wl1271 *wl) in wl18xx_enable_interrupts() argument
988 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask); in wl18xx_enable_interrupts()
992 wlcore_enable_interrupts(wl); in wl18xx_enable_interrupts()
994 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, in wl18xx_enable_interrupts()
1002 wlcore_disable_interrupts(wl); in wl18xx_enable_interrupts()
1008 static int wl18xx_boot(struct wl1271 *wl) in wl18xx_boot() argument
1012 ret = wl18xx_pre_boot(wl); in wl18xx_boot()
1016 ret = wl18xx_pre_upload(wl); in wl18xx_boot()
1020 ret = wlcore_boot_upload_firmware(wl); in wl18xx_boot()
1024 ret = wl18xx_set_mac_and_phy(wl); in wl18xx_boot()
1028 wl->event_mask = BSS_LOSS_EVENT_ID | in wl18xx_boot()
1047 wl->ap_event_mask = MAX_TX_FAILURE_EVENT_ID; in wl18xx_boot()
1049 ret = wlcore_boot_run_firmware(wl); in wl18xx_boot()
1053 ret = wl18xx_enable_interrupts(wl); in wl18xx_boot()
1059 static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr, in wl18xx_trigger_cmd() argument
1062 struct wl18xx_priv *priv = wl->priv; in wl18xx_trigger_cmd()
1067 return wlcore_write(wl, cmd_box_addr, priv->cmd_buf, in wl18xx_trigger_cmd()
1071 static int wl18xx_ack_event(struct wl1271 *wl) in wl18xx_ack_event() argument
1073 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG, in wl18xx_ack_event()
1077 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks) in wl18xx_calc_tx_blocks() argument
1084 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc, in wl18xx_set_tx_desc_blocks() argument
1091 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc, in wl18xx_set_tx_desc_data_len() argument
1097 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) in wl18xx_set_tx_desc_data_len()
1110 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc) in wl18xx_get_rx_buf_align() argument
1118 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data, in wl18xx_get_rx_packet_len() argument
1130 static void wl18xx_tx_immediate_completion(struct wl1271 *wl) in wl18xx_tx_immediate_completion() argument
1132 wl18xx_tx_immediate_complete(wl); in wl18xx_tx_immediate_completion()
1135 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk) in wl18xx_set_host_cfg_bitmap() argument
1143 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) { in wl18xx_set_host_cfg_bitmap()
1149 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) { in wl18xx_set_host_cfg_bitmap()
1154 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap, in wl18xx_set_host_cfg_bitmap()
1163 static int wl18xx_hw_init(struct wl1271 *wl) in wl18xx_hw_init() argument
1166 struct wl18xx_priv *priv = wl->priv; in wl18xx_hw_init()
1173 ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE); in wl18xx_hw_init()
1178 ret = wl18xx_acx_dynamic_fw_traces(wl); in wl18xx_hw_init()
1183 ret = wl18xx_acx_set_checksum_state(wl); in wl18xx_hw_init()
1191 static void wl18xx_convert_fw_status(struct wl1271 *wl, void *raw_fw_status, in wl18xx_convert_fw_status() argument
1228 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl, in wl18xx_set_tx_desc_csum() argument
1258 static void wl18xx_set_rx_csum(struct wl1271 *wl, in wl18xx_set_rx_csum() argument
1266 static bool wl18xx_is_mimo_supported(struct wl1271 *wl) in wl18xx_is_mimo_supported() argument
1268 struct wl18xx_priv *priv = wl->priv; in wl18xx_is_mimo_supported()
1282 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl, in wl18xx_sta_get_ap_rate_mask() argument
1294 } else if (wl18xx_is_mimo_supported(wl)) { in wl18xx_sta_get_ap_rate_mask()
1302 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl, in wl18xx_ap_get_mimo_wide_rate_mask() argument
1314 } else if (wl18xx_is_mimo_supported(wl) && in wl18xx_ap_get_mimo_wide_rate_mask()
1353 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver) in wl18xx_get_pg_ver() argument
1359 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); in wl18xx_get_pg_ver()
1363 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse); in wl18xx_get_pg_ver()
1369 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse); in wl18xx_get_pg_ver()
1383 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse); in wl18xx_get_pg_ver()
1395 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); in wl18xx_get_pg_ver()
1449 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev) in wl18xx_conf_init() argument
1451 struct platform_device *pdev = wl->pdev; in wl18xx_conf_init()
1453 struct wl18xx_priv *priv = wl->priv; in wl18xx_conf_init()
1455 if (wl18xx_load_conf_file(dev, &wl->conf, &priv->conf, in wl18xx_conf_init()
1460 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl->conf)); in wl18xx_conf_init()
1469 static int wl18xx_plt_init(struct wl1271 *wl) in wl18xx_plt_init() argument
1474 if (wl->plt_mode == PLT_FEM_DETECT) { in wl18xx_plt_init()
1479 ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT); in wl18xx_plt_init()
1483 return wl->ops->boot(wl); in wl18xx_plt_init()
1486 static int wl18xx_get_mac(struct wl1271 *wl) in wl18xx_get_mac() argument
1491 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); in wl18xx_get_mac()
1495 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1); in wl18xx_get_mac()
1499 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2); in wl18xx_get_mac()
1504 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) + in wl18xx_get_mac()
1506 wl->fuse_nic_addr = (mac1 & 0xffffff); in wl18xx_get_mac()
1508 if (!wl->fuse_oui_addr && !wl->fuse_nic_addr) { in wl18xx_get_mac()
1513 wl->fuse_oui_addr = (mac[0] << 16) + (mac[1] << 8) + mac[2]; in wl18xx_get_mac()
1514 wl->fuse_nic_addr = (mac[3] << 16) + (mac[4] << 8) + mac[5]; in wl18xx_get_mac()
1518 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]); in wl18xx_get_mac()
1524 static int wl18xx_handle_static_data(struct wl1271 *wl, in wl18xx_handle_static_data() argument
1530 strncpy(wl->chip.phy_fw_ver_str, static_data_priv->phy_version, in wl18xx_handle_static_data()
1531 sizeof(wl->chip.phy_fw_ver_str)); in wl18xx_handle_static_data()
1534 wl->chip.phy_fw_ver_str[sizeof(wl->chip.phy_fw_ver_str) - 1] = '\0'; in wl18xx_handle_static_data()
1541 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem) in wl18xx_get_spare_blocks() argument
1543 struct wl18xx_priv *priv = wl->priv; in wl18xx_get_spare_blocks()
1552 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd, in wl18xx_set_key() argument
1557 struct wl18xx_priv *priv = wl->priv; in wl18xx_set_key()
1567 ret = wlcore_set_key(wl, cmd, vif, sta, key_conf); in wl18xx_set_key()
1595 ret = wl18xx_set_host_cfg_bitmap(wl, in wl18xx_set_key()
1598 ret = wl18xx_set_host_cfg_bitmap(wl, in wl18xx_set_key()
1605 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl, in wl18xx_pre_pkt_send() argument
1608 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) { in wl18xx_pre_pkt_send()
1612 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf + in wl18xx_pre_pkt_send()
1624 static void wl18xx_sta_rc_update(struct wl1271 *wl, in wl18xx_sta_rc_update() argument
1645 wl18xx_acx_peer_ht_operation_mode(wl, wlvif->sta.hlid, wide); in wl18xx_sta_rc_update()
1650 static int wl18xx_set_peer_cap(struct wl1271 *wl, in wl18xx_set_peer_cap() argument
1655 return wl18xx_acx_set_peer_cap(wl, ht_cap, allow_ht_operation, in wl18xx_set_peer_cap()
1659 static bool wl18xx_lnk_high_prio(struct wl1271 *wl, u8 hlid, in wl18xx_lnk_high_prio() argument
1664 (struct wl18xx_fw_status_priv *)wl->fw_status->priv; in wl18xx_lnk_high_prio()
1677 if (test_bit(hlid, &wl->fw_fast_lnk_map) && in wl18xx_lnk_high_prio()
1678 !test_bit(hlid, &wl->ap_fw_ps_map)) in wl18xx_lnk_high_prio()
1686 static bool wl18xx_lnk_low_prio(struct wl1271 *wl, u8 hlid, in wl18xx_lnk_low_prio() argument
1691 (struct wl18xx_fw_status_priv *)wl->fw_status->priv; in wl18xx_lnk_low_prio()
1701 else if (test_bit(hlid, &wl->fw_fast_lnk_map) && in wl18xx_lnk_low_prio()
1702 !test_bit(hlid, &wl->ap_fw_ps_map)) in wl18xx_lnk_low_prio()
1710 static u32 wl18xx_convert_hwaddr(struct wl1271 *wl, u32 hwaddr) in wl18xx_convert_hwaddr() argument
1715 static int wl18xx_setup(struct wl1271 *wl);
1919 static int wl18xx_setup(struct wl1271 *wl) in wl18xx_setup() argument
1921 struct wl18xx_priv *priv = wl->priv; in wl18xx_setup()
1928 wl->rtable = wl18xx_rtable; in wl18xx_setup()
1929 wl->num_tx_desc = WL18XX_NUM_TX_DESCRIPTORS; in wl18xx_setup()
1930 wl->num_rx_desc = WL18XX_NUM_RX_DESCRIPTORS; in wl18xx_setup()
1931 wl->num_links = WL18XX_MAX_LINKS; in wl18xx_setup()
1932 wl->max_ap_stations = WL18XX_MAX_AP_STATIONS; in wl18xx_setup()
1933 wl->iface_combinations = wl18xx_iface_combinations; in wl18xx_setup()
1934 wl->n_iface_combinations = ARRAY_SIZE(wl18xx_iface_combinations); in wl18xx_setup()
1935 wl->num_mac_addr = WL18XX_NUM_MAC_ADDRESSES; in wl18xx_setup()
1936 wl->band_rate_to_idx = wl18xx_band_rate_to_idx; in wl18xx_setup()
1937 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX; in wl18xx_setup()
1938 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0; in wl18xx_setup()
1939 wl->fw_status_len = sizeof(struct wl18xx_fw_status); in wl18xx_setup()
1940 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv); in wl18xx_setup()
1941 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics); in wl18xx_setup()
1942 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv); in wl18xx_setup()
1945 wl->num_rx_desc = num_rx_desc_param; in wl18xx_setup()
1947 ret = wl18xx_conf_init(wl, wl->dev); in wl18xx_setup()
2014 if (wl18xx_is_mimo_supported(wl)) in wl18xx_setup()
2015 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ, in wl18xx_setup()
2018 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ, in wl18xx_setup()
2022 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ, in wl18xx_setup()
2025 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ, in wl18xx_setup()
2027 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ, in wl18xx_setup()
2030 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ, in wl18xx_setup()
2032 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ, in wl18xx_setup()
2042 wl->enable_11a = (priv->conf.phy.number_of_assembled_ant5 != 0); in wl18xx_setup()
2049 struct wl1271 *wl; in wl18xx_probe() local
2062 wl = hw->priv; in wl18xx_probe()
2063 wl->ops = &wl18xx_ops; in wl18xx_probe()
2064 wl->ptable = wl18xx_ptable; in wl18xx_probe()
2065 ret = wlcore_probe(wl, pdev); in wl18xx_probe()
2072 wlcore_free_hw(wl); in wl18xx_probe()